View PEB20525F_1660691.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

serocco-h 2 channel serial optimized communication controller for hdlc/ppp peb 20525 version 1.2 pef 20525 version 1.2 never stop thinking. datacom data sheet, ds 1, sep. 2000
edition 2000-09-14 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 9/14/00. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
serocco-h 2 channel serial optimized communication controller for hdlc/ppp peb 20525 version 1.2 pef 20525 version 1.2 never stop thinking. datacom data sheet, ds 1, sep. 2000
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 20525 revision history: 2000-09-14 ds 1 previous version: passat v1.1 preliminary data sheet, 09.99, ds2 page (previous version) page (current version) subjects (major changes since last revision) 33-35 36-38 correction: signal ?osr? is multiplexed with signal ?cd?, signal ?ost? is multiplexed with ?cts ? (was vice versa) 81 84 corrected hdlc receive address recognition table n.a. 232, 235 added timing diagram for external dma support signals n.a. 232 added address timing diagram for intel multiplexed mode (signal ale) 222 226 chapter "electrical characteristics" updated with final characterization results.
peb 20525 pef 20525 table of contents page data sheet 5 2000-09-14 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.1 system integration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.3.2 serial configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.4 differences between serocco-h and the hscx/escc family . . . . . . 25 1.4.1 enhancements to the hscx serial core . . . . . . . . . . . . . . . . . . . . . . . . 25 1.4.2 simplifications to the hscx serial core . . . . . . . . . . . . . . . . . . . . . . . . 25 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.1 pin diagram p-lfbga-80-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2 pin diagram p-tqfp-100-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 serial communication controller (scc) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.1 protocol modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.2 scc fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.2.1 scc transmit fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.2.2 scc receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2.3 scc fifo access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.3 clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.3.1 clock mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.2.3.2 clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.3.3 clock mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.3.4 clock mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.3.5 clock mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.3.6 clock mode 5a (time slot mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2.3.7 clock mode 5b (octet sync mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.2.3.8 clock mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.2.3.9 clock mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.2.4 baud rate generator (brg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.2.5 clock recovery (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.2.6 scc timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.2.7 scc serial bus configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.8 serial bus access procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.9 serial bus collisions and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.10 serial bus access priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2.11 serial bus configuration timing modes . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2.12 functions of signal rts in hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2.13 data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
peb 20525 pef 20525 table of contents page data sheet 6 2000-09-14 3.2.13.1 nrz and nrzi encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.2.13.2 fm0 and fm1 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.2.13.3 manchester encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.2.14 modem control signals (rts, cts, cd) . . . . . . . . . . . . . . . . . . . . . . . 77 3.2.14.1 rts/cts handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2.14.2 carrier detect (cd) receiver control . . . . . . . . . . . . . . . . . . . . . . . . 78 3.2.15 local loop test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.4 external dma controller support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.5 interrupt architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.6 general purpose port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6.1 gpp functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6.2 gpp interrupt indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4 detailed protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1 hdlc/sdlc protocol modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1.0.1 automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.1.0.2 address mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1.0.3 address mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1.0.4 address mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1.1 hdlc receive data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1.2 receive address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1.3 hdlc transmit data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1.4 shared flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1.5 one bit insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1.6 preamble transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1.7 crc generation and checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.1.8 receive length check feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2 point-to-point protocol (ppp) modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.1 bit synchronous ppp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.2 octet synchronous ppp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.3 data transparency in ppp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3 extended transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4 procedural support (layer-2 functions) . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.4.1 full-duplex lapb/lapd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.4.2 half-duplex sdlc-nrm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.4.3 signaling system #7 (ss7) operation . . . . . . . . . . . . . . . . . . . . . . . . . 103 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.2.1 global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.2.2 channel specific scc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
peb 20525 pef 20525 table of contents page data sheet 7 2000-09-14 5.2.3 channel specific dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 5.2.4 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 6 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.2.1 data transmission (interrupt driven) . . . . . . . . . . . . . . . . . . . . . . . . . . 215 6.2.2 data reception (interrupt driven) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.3 external dma supported mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 6.3.1 data transmission (with external dma support) . . . . . . . . . . . . . . . . 219 6.3.2 data reception (with external dma support) . . . . . . . . . . . . . . . . . . . 222 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 7.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 7.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 7.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 7.5 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 7.6 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 7.7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.7.1 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.7.1.1 microprocessor interface clock timing . . . . . . . . . . . . . . . . . . . . . . 230 7.7.1.2 infineon/intel bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.7.1.3 motorola bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.7.2 pcm serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.7.2.1 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.7.2.2 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 7.7.2.3 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.7.2.4 clock mode 1 strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 7.7.2.5 clock mode 4 gating timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 7.7.2.6 clock mode 5 frame synchronisation timing . . . . . . . . . . . . . . . . . 243 7.7.3 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 7.7.4 jtag-boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 8.1 jtag boundary scan interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
peb 20525 pef 20525 list of figures page data sheet 8 2000-09-14 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 2 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3 system integration with external dma controller . . . . . . . . . . . . . . . . 22 figure 4 point-to-point configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5 point-to-multipoint bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6 multimaster bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7 pin configuration p-lfbga-80-2 package . . . . . . . . . . . . . . . . . . . . . 26 figure 8 pin configuration p-tqfp-100-3 package . . . . . . . . . . . . . . . . . . . . . 27 figure 9 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 10 scc transmit fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 11 scc receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 12 xfifo/rfifo word access (intel mode) . . . . . . . . . . . . . . . . . . . . . . 46 figure 13 xfifo/rfifo word access (motorola mode) . . . . . . . . . . . . . . . . . . . 46 figure 14 clock supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 15 clock mode 0a/0b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 16 clock mode 1 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17 clock mode 2a/2b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 18 clock mode 3a/3b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 19 clock mode 4 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 20 selecting one time-slot of programmable delay and width . . . . . . . . . 57 figure 21 selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 59 figure 22 clock mode 5a configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 23 clock mode 5a "continuous mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 24 clock mode 5a "non continuous mode" . . . . . . . . . . . . . . . . . . . . . . . 62 figure 25 selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 64 figure 26 clock mode 5b configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 27 clock mode 6a/6b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 28 clock mode 7a/7b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 29 dpll algorithm (nrz and nrzi encoding, phase shift enabled) . . . 70 figure 30 dpll algorithm (nrz and nrzi encoding, phase shift disabled) . . . 70 figure 31 dpll algorithm for fm0, fm1 and manchester encoding . . . . . . . . . 71 figure 32 request-to-send in bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 33 nrz and nrzi data encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 34 fm0 and fm1 data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 35 manchester data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 36 rts/cts handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37 scc test loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 38 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 39 hdlc receive data processing in 16 bit automode . . . . . . . . . . . . . . 86 figure 40 hdlc receive data processing in 8 bit automode . . . . . . . . . . . . . . . 86 figure 41 hdlc receive data processing in address mode 2 (16 bit). . . . . . . . 86 figure 42 hdlc receive data processing in address mode 2 (8 bit). . . . . . . . . 87
peb 20525 pef 20525 list of figures page data sheet 9 2000-09-14 figure 43 hdlc receive data processing in address mode 1 . . . . . . . . . . . . . . 87 figure 44 hdlc receive data processing in address mode 0 . . . . . . . . . . . . . . 87 figure 45 scc transmit data flow (hdlc modes) . . . . . . . . . . . . . . . . . . . . . . 89 figure 46 ppp mapping/unmapping example. . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 47 processing of received frames in auto mode . . . . . . . . . . . . . . . . . . 97 figure 48 timer procedure/poll cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 49 transmission/reception of i-frames and flow control . . . . . . . . . . . 100 figure 50 flow control: reception of s-commands and protocol errors . . . . . 100 figure 51 no data to send: data reception/transmission . . . . . . . . . . . . . . . . 103 figure 52 data transmission (without error), data transmission (with error) . . 103 figure 53 interrupt driven data transmission (flow diagram) . . . . . . . . . . . . . 216 figure 54 interrupt driven data reception (flow diagram) . . . . . . . . . . . . . . . . 218 figure 55 dma transmit (single buffer per packet) . . . . . . . . . . . . . . . . . . . . . 220 figure 56 fragmented dma transmission (multiple buffers per packet) . . . . . 221 figure 57 dma receive (single buffer per packet) . . . . . . . . . . . . . . . . . . . . . . 223 figure 58 fragmented reception per dma (example) . . . . . . . . . . . . . . . . . . . 224 figure 59 fragmented reception sequence (example) . . . . . . . . . . . . . . . . . . 225 figure 60 input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 61 microprocessor interface clock timing . . . . . . . . . . . . . . . . . . . . . . . 230 figure 62 infineon/intel read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 63 infineon/intel write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 64 infineon/intel dma read cycle timing . . . . . . . . . . . . . . . . . . . . . . . 232 figure 65 infineon/intel dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . 232 figure 66 infineon/intel multiplexed address timing . . . . . . . . . . . . . . . . . . . . . 232 figure 67 motorola read cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 68 motorola write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 69 motorola dma read cycle timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 70 motorola dma write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 71 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 72 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 73 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 figure 74 clock mode 1 strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 75 clock mode 4 receive gating timing . . . . . . . . . . . . . . . . . . . . . . . . 242 figure 76 clock mode 4 transmit gating timing. . . . . . . . . . . . . . . . . . . . . . . . 242 figure 77 clock mode 5 frame synchronisation timing . . . . . . . . . . . . . . . . . . 243 figure 78 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 figure 79 jtag-boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 80 block diagram of test access port and boundary scan unit . . . . . . 246
peb 20525 pef 20525 list of tables page data sheet 10 2000-09-14 table 1 microprocessor bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 2 external dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3 serial port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 4 general purpose pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5 test interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 7 overview of clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 8 clock modes of the sccs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9 brrl/brrh register and bit-fields . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 10 data bus access 16-bit intel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 11 data bus access 16-bit motorola mode. . . . . . . . . . . . . . . . . . . . . . . . 80 table 12 protocol mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 13 address comparison overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 14 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 15 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 16 status information after rme interupt . . . . . . . . . . . . . . . . . . . . . . . . 217 table 17 dma terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 18 capacitances ta = 25 c; vdd3 = 3.3 v 0.3 v, vss = 0 v . . . . . . . . . . . . . . . . . 228 table 19 thermal package characteristics p-tqfp-100-3 . . . . . . . . . . . . . . . 229 table 20 thermal package characteristics p-lfbga-80-2 . . . . . . . . . . . . . . . 229 table 21 microprocessor interface clock timing . . . . . . . . . . . . . . . . . . . . . . . 230 table 22 infineon/intel bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . 233 table 23 motorola bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 table 24 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 table 25 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 table 26 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 27 clock mode 1 strobe timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table 28 clock mode 4 gating timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 29 clock mode 5 frame synchronisation timing . . . . . . . . . . . . . . . . . . 243 table 30 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 31 jtag-boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 32 boundary scan sequence of serocco-h . . . . . . . . . . . . . . . . . . . 247 table 33 boundary scan test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
peb 20525 pef 20525 list of registers page data sheet 11 2000-09-14 register 1 gcmdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 register 2 gmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 register 3 gstar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 register 4 gpdirl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 register 5 gpdirh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 register 6 gpdatl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 register 7 gpdath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 register 8 gpiml . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 register 9 gpimh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 register 10 gpisl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 register 11 gpish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 register 12 dcmdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 register 13 disr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 register 14 dimr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 register 15 fifol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 register 16 fifoh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 register 17 starl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 register 18 starh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 register 19 cmdrl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 register 20 cmdrh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 register 21 ccr0l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 register 22 ccr0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 register 23 ccr1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 register 24 ccr1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 register 25 ccr2l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 register 26 ccr2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 register 27 ccr3l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 register 28 ccr3h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 register 29 preamb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 register 30 accm0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 register 31 accm1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 register 32 accm2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 register 33 accm3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 register 34 udac0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 register 35 udac1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 register 36 udac2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 register 37 udac3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 register 38 ttsa0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 register 39 ttsa1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 register 40 ttsa2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 register 41 ttsa3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 register 42 rtsa0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
peb 20525 pef 20525 list of registers page data sheet 12 2000-09-14 register 43 rtsa1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 register 44 rtsa2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 register 45 rtsa3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 register 46 pcmtx0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 register 47 pcmtx1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 register 48 pcmtx2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 register 49 pcmtx3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 register 50 pcmrx0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 register 51 pcmrx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 register 52 pcmrx2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 register 53 pcmrx3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 register 54 brrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 register 55 brrh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 register 56 timr0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 register 57 timr1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 register 58 timr2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register 59 timr3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register 60 xad1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register 61 xad2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register 62 ral1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 register 63 rah1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 register 64 ral2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 register 65 rah2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 register 66 amral1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 register 67 amrah1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 register 68 amral2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 register 69 amrah2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 register 70 rlcrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 register 71 rlcrh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 register 72 isr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 register 73 isr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 register 74 isr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 register 75 imr0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 register 76 imr1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 register 77 imr2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 register 78 rsta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 register 79 xbcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 register 80 xbch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 register 81 rmbsl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 register 82 rmbsh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 register 83 rbcl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 register 84 rbch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
peb 20525 pef 20525 list of registers page data sheet 13 2000-09-14 register 85 ver0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 register 86 ver1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 register 87 ver2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 register 88 ver3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
peb 20525 pef 20525 data sheet 14 2000-09-14 preface the 2 channel serial optimized communication controller for hdlc/ppp peb 20525 (serocco-h) is a protocol controller for a wide range of data communication and telecommunication applications. this document provides complete reference information on hardware and software related issues as well as on general operation. organization of this document this data sheet is divided into 9 chapters. it is organized as follows: chapter 1 , introduction gives a general description of the product, lists the key features, and presents some typical applications. chapter 2 , pin descriptions lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 , functional overview this chapter provides detailed descriptions of all serocco-h internal functional blocks. chapter 4 , detailed protocol description gives a detailed description of all protocols supported by the serial communication controllers sccs. chapter 5 , register description gives a detailed description of all serocco-h on chip registers. chapter 6 , programming provides programming help for serocco-h initialization procedure and operation. chapter 7 , electrical characteristics gives a detailed description of all electrical dc and ac characteristics and provides timing diagrams and values for all interfaces. chapter 8 , test modes gives a detailed description of the jtag boundary scan unit. chapter 9 , package outlines
peb 20525 pef 20525 data sheet 15 2000-09-14 your comments we welcome your comments on this document. we are continuously trying improving our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (serocco-h), device number (peb 20525, pef 20525), device version (version 1.2), and in the body of your e-mail: document type (data sheet), issue date (2000-09-14) and document revision number (ds 1).
peb 20525 pef 20525 introduction data sheet 16 2000-09-14 1 introduction the serocco-h is a serial communication controller with two independent serial channels 1) . the serial channels are derived from updated protocol logic of the escc and dscc4 device family providing a large set of protocol support and variety in serial interface configuration. this allows easy integration to different environments and applications. a generic 8- or 16-bit multiplexed/demultiplexed slave interface provides fast device access with low bus utilization and easy software handshaking (in the p-lfbga-80-2 package only an 8-bit data bus is provided). dma handshake control signals allow connection to an external dma controller. large on-chip fifos of 64 byte capacity per port and direction in combination with enhanced threshold control mechanisms allow decoupling of traffic requirements on host bus and serial interfaces with little exception probabilities such as data underruns or overflows. each of the two serial communication controllers (scc) contains an independent baud rate generator, dpll and programmable protocol processing (hdlc, ppp). data rates of up to 12.5 mbit/s (2 mbit/s in dpll assisted modes) are supported. the channels can also handle a large set of layer-2 protocol functions (lapd, ss7) reducing bus and host cpu load. two channel specific timers are provided to support protocol functions. 1) the serial channels are also called ? ports ? or ? cores ? depending on the context.
2 channel serial optimized communication controller for hdlc/ppp serocco-h peb 20525 pef 20525 data sheet 1-17 2000-09-14 version 1.2 cmos type package peb 20525, pef 20525 p-tqfp-100-3 p-lfbga-80-2 1.1 features serial communication controllers (sccs) two independent channels full duplex data rates on each channel of up to 12.5 mbit/s sync - 2 mbit/s with dpll 64 bytes deep receive fifo per scc 64 bytes deep transmit fifo per scc serial interface on-chip clock generation or external clock sources on-chip dplls for clock recovery baud rate generator clock gating signals clock gapping capability programmable time-slot capability for connection to tdm interfaces (e.g. t1, e1) nrz, nrzi, fm and manchester data encoding optional data flow control using modem control lines (rts , cts , cd) support of bus configuration by collision detection and resolution bit processor functions hdlc/sdlc protocol modes ? automatic flag detection and transmission ? shared opening and closing flag ? generation of interframe-time fill ? 1 ? s or flags ? detection of receive line status ? zero bit insertion and deletion p-tqfp-128-1 p-tqfp-100-3 p-lfbga-80-2
peb 20525 pef 20525 introduction data sheet 18 2000-09-14 ? crc generation and checking (crc-ccitt or crc-32) ? transparent crc option per channel and/or per frame ? programmable preamble (8 bit) with selectable repetition rate ? error detection (abort, long frame, crc error, short frames) bit synchronous ppp mode ? bit oriented transmission of hdlc frame (flag, data, crc, flag) ? zero bit insertion/deletion ? 15 consecutive ? 1 ? bits abort sequence octet synchronous ppp mode ? octet oriented transmission of hdlc frame (flag, data, crc, flag) ? programmable character map of 32 hard-wired characters (00 h -1f h ) ? four programmable characters for additional mapping ? insertion/deletion of control-escape character (7d h ) for mapped characters extended transparent mode ? fully bit transparent (no framing, no bit manipulation) ? octet-aligned transmission and reception protocol and mode independent ? data bit inversion ? data overflow and underrun detection ? timer protocol support address recognition modes ? no address recognition (address mode 0) ? 8-bit (high byte) address recognition (address mode 1) ? 8-bit (low byte) or 16-bit (high and low byte) address recognition (address mode 2) hdlc automode ? 8-bit or 16-bit address generation/recognition ? support of lapb/lapd ? automatic handling of s- and i-frames ? automatic processing of control byte(s) ? modulo-8 or modulo-128 operation ? programmable time-out and retry conditions ? sdlc normal response mode (nrm) operation for slave signaling system #7 (ss7) support ? detection of fisus, msus and lssus ? unchanged fill-in signaling units (fisus) not forwarded ? automatic generation of fisus in transmit direction (incl. sequence number) ? counting of errored signaling units optional dtack /ready controlled cycles
peb 20525 pef 20525 introduction data sheet 19 2000-09-14 microprocessor interface 8-bit bus interface (p-lfbga-80-2 package) 8/16-bit bus interface (p-tqfp-100-3 package) multiplexed and de-multiplexed address/data bus intel/motorola style asynchronous interface maskable interrupts for each channel general purpose port (gpp) pins (up to 3 in p-lfbga-80-2, up to 7 in p-tqfp-100- 3 package) general 3.3v power supply with 5v tolerant inputs low power consumption power safe features p-tqfp-100-3 package (thermal resistance: r ja = 42 k/w) small p-lfbga-80-2 package (thermal resistance: r ja = 51 k/w)
peb 20525 pef 20525 introduction data sheet 20 2000-09-14 1.2 logic symbol figure 1 logic symbol v ss v dd3 test tck tms tdi tdo trst jtag test interface txd a rxd a rts a /txclko a cts a /cxd a /tcg a /ost a cd a /fsc a /rcg a /osr a txclk a rxclk a serial channel a serocco-h peb 20525 pef 20525 xtal1 xtal2 txd b rxd b rts b /txclko b cts b /cxd b /tcg b /ost b cd b /fsc b /rcg b /osr b txclk b rxclk b serial channel b drt a drr a dack a drt b drr b dack b external dma interface 1) intel bus mode 2) motorola bus mode a(7:0) microprocessor interface d(15:8) 3) ale 1) lds 2) uds 2) 3) rd 1) wr 1) int/int clk reset cs dtack bhe 1) 3) r/w 2) d(7:0) 3) 16-bit mode (tqfp-100 package only) gp n general purpose port
peb 20525 pef 20525 introduction data sheet 21 2000-09-14 1.3 typical applications serocco-h devices can be used in lan-wan inter-networking applications such as routers, switches and trunk cards and support the common v.35, isdn bri (s/t) and rfc1662 standards. its new features provide powerful hardware and software interfaces to develop high performance systems. 1.3.1 system integration example figure 2 system integration . . . . . . . . . . . . transceiver, framer system bus cpu ram bank serocco-h peb 20525 pef 20525
peb 20525 pef 20525 introduction data sheet 22 2000-09-14 figure 3 system integration with external dma controller . . . . . . . . . . . . transceiver, framer system bus cpu ram bank dma controller serocco-h peb 20525 pef 20525
peb 20525 pef 20525 introduction data sheet 23 2000-09-14 1.3.2 serial configuration examples serocco-h supports a variety of serial configurations at layer-1 and layer-2 level. the outstanding variety of clock modes supporting a large number of combinations of external and internal clock sources allows easy integration in application environments. figure 4 point-to-point configuration . . . . . . . . . . . . . . . . . . . . . . . . txd rxd rxd txd serial transmission optional modem control signals layer-2 lapd/b or ss7 protocol support serocco-h peb 20525 pef 20525 serocco-h peb 20525 pef 20525
peb 20525 pef 20525 introduction data sheet 24 2000-09-14 figure 5 point-to-multipoint bus configuration figure 6 multimaster bus configuration . . . . . . . . . . . . . . . . . . . . . . . . txd rxd rxd txd . . . . . . . . . . . . rxd txd ... . . . . . . . . . . . . txd cxd cxd cxd rxd master slave n slave 2 slave 1 layer-1 collision detection or layer-2 sdlc-nrm operation serocco-h peb 20525 pef 20525 serocco-h peb 20525 pef 20525 serocco-h peb 20525 pef 20525 . . . . . . . . . . . . . . . . . . . . . . . . txd rxd rxd txd . . . . . . . . . . . . rxd txd ... cxd cxd cxd master n master 2 master 1 layer-1 collision detection serocco-h peb 20525 pef 20525 serocco-h peb 20525 pef 20525 serocco-h peb 20525 pef 20525
peb 20525 pef 20525 introduction data sheet 25 2000-09-14 1.4 differences between serocco-h and the hscx/escc family this chapter is useful for all being familiar with the hscx/escc family. 1.4.1 enhancements to the hscx serial core the serocco-h scc cores contain the core logic of the hscx as the heart of the device. some enhancements are incorporated in the sccs. these are: octet- and bit synchronous ppp protocol support as in rfc-1662 signaling system #7 (ss7) support 4-kbyte packet length byte counter enhanced address filtering (16-bit maskable) enhanced time slot assigner support of high data rates (12.5 mbit/s) 1.4.2 simplifications to the hscx serial core the following features of the hscx core have been removed: extended transparent mode 0 (this mode provided octet buffered data reception without usage of fifos; serocco-h supports octet buffered reception via appropriate threshold configurations for the scc receive fifos) master clock mode
peb 20525 pef 20525 pin descriptions data sheet 26 2000-09-14 2 pin descriptions 2.1 pin diagram p-lfbga-80-2 (top view) figure 7 pin configuration p-lfbga-80-2 package drta vss test2 d6 vss d2 vdd ready# dtack# rd# drra vdd d7 d4 d3 vss wr# tms vss vdd dacka# drrb/ gp1 test1 vdd d1 clk cs# r/w# rtsb# vss dackb# gp2 d5 d0 vss ds#/ bhe#/ lds# vdd bm/ ale vss rxdb vdd drtb/ gp0 vss a1 a2 a0/ ble#/ uds# txclkb rxclkb vdd txdb xtal2 txda vdd a4 a3 vss cdb/ fscb/ rcgb#/ osrb vss xtal1 cda/ fsca/ rcga#/ osra txclka a6 vss a5 tdi trst# tck vssa ctsa#/ cxda/ tcga#/ osta rxclka vss reset# a7 tdo vdd ctsb#/ cxdb/ tcgb#/ ostb vdda rxda vdd rtsa# int/ int# vdd a b c d e f g h j 1 2 3 4 5 6 7 8 9 p-lfbga-80-2
peb 20525 pef 20525 pin descriptions data sheet 27 2000-09-14 2.2 pin diagram p-tqfp-100-3 (top view) figure 8 pin configuration p-tqfp-100-3 package tdo tck vdd vss ctsb#/cxdb/tcgb#/ostb vssa xtal2 xtal1 vdda ctsa#/cxda/tcga#/osta cda/fsca/rcga#/osra rxda rxclka txda vdd vss txclka rtsa# reset# int/int# vdd vss gp10 gp9 gp8 vss vdd vss vdd tms r/w# ds#/bhe#/lds# cs# bm/ale vss vdd a0/ble#/uds# a1 a2 a3 vdd vss width a4 a5 a6 a7 vss vdd gp6 d11 d10 d9 d8 vss vdd test2 test1 d7 d6 d5 d4 vss vdd d3 d2 d1 d0 vss vdd clk ready#/dtack# wr# rd# vss vdd vss d12 d13 d14 d15 vdd vss drta dacka# drra drrb/gp1 drtb/gp0 dackb#/gp2 rtsb# rxdb vdd vss rxclkb txdb txclkb cdb/fscb/rcgb#/osrb vdd trst# tdi 75 70 65 60 55 80 85 90 95 100 1 5 10 15 20 25 50 45 40 35 30 p-tqfp-100-3
peb 20525 pef 20525 pin descriptions data sheet 28 2000-09-14 2.3 pin definitions and functions table 1 microprocessor bus interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 - - - - - - - - c8 d9 d6 d8 e8 f9 f7 e6 81 80 79 78 75 74 73 72 67 66 65 64 61 60 59 58 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i/o data bus the data bus lines are bi-directional tri-state lines which interface with the system ? s data bus. the serocco-h in the p-lfbga-80-2 package does not support 16-bit bus modes. j2 g3 j3 h4 j4 h5 g5 29 30 31 32 36 37 38 a7 a6 a5 a4 a3 a2 a1 i i i i i i i address bus these pins connect to the system ? s address bus to select one of the internal registers for read or write.
peb 20525 pef 20525 pin descriptions data sheet 29 2000-09-14 j5 39 a0 ble uds i i i address line a0 (8-bit modes) in motorola and in intel 8-bit mode this signal represents the least significant address line. byte low enable (16-bit intel bus mode) this signal indicates a data transfer on the lower byte of the data bus (d7..d0). together with signal bhe the type of bus access is determined (byte or word access at even or odd address). upper data strobe (16-bit motorola bus mode) this active low strobe signal serves to control read/write operations. together with signal lds the type of bus access is determined. j6 42 bm ale i i bus mode ? bm = static ? 1 ? for operation in motorola bus mode (de-multiplexed). ? bm = static ? 0 ? for operation in intel bus mode with de-multiplexed address and data buses. ? pin bm/ale has the function of an address latch enable (ale) for operation in intel bus mode with a multiplexed address/data bus. a falling edge on this pin selects intel multiplexed bus mode. address latch enable (mux ? ed intel bus) the address is latched by the serocco-h with the falling edge of ale. the address input pins a(7:0) pins a(15:0) must be externally connected to the data bus pins d(7:0)d(15:0). for operation of the 8-bit serocco-h (p- lfbga-80-2 package) in a 16-bit environment, a(7:0) should be connected to address/data lines ad(8:1) of the external bus. d(7:0) interface to ad(7:0) of the external bus. table 1 microprocessor bus interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 30 2000-09-14 g6 44 ds bhe l ds i i i data strobe (8-bit motorola bus mode only) this active low strobe signal serves to control read/write operations. bus high enable (16-bit intel bus mode only) this signal indicates a data transfer on the upper byte of the data bus (d15..d8). in 8-bit intel bus mode this signal has no function. lower data strobe (16-bit motorola bus mode) this active low strobe signal serves to control read/write operations. together with signal uds the type of bus access is determined (byte or word access at even or odd address). in 8-bit intel bus mode, a pull-up resistor to v dd3 is recommended on this pin. j9 52 rd i read strobe (intel bus mode only) this signal indicates a read operation. the current bus master is able to accept data on lines d(7:0) / d(15:0) during an active rd signal. in motorola bus mode, a pull-up resistor to v dd3 is recommended on this pin. j7 45 r/w i read/write enable (motorola bus mode) this signal distinguishes between read and write operation. as an input it must be valid during data strobe (ds ). in intel bus mode, a pull-up resistor to v dd3 is recommended on this pin. h7 43 cs i chip select a low signal selects serocco-h for read/write operations. table 1 microprocessor bus interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 31 2000-09-14 g8 53 wr i write strobe (intel bus mode only) this signal indicates a write operation. the current bus master presents valid data on lines d(7:0) / d(15:0) during an active wr signal. in motorola bus mode, a pull-up resistor to v dd3 is recommended on this pin. -33widthi width of bus interface a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using ble and bhe (intel bus mode) or lds and uds (motorola bus mode) in p-lfbga-80-2 package this signal is not available, since only 8 bit bus width is supported. g7 55 clk i clock the system clock for serocco-h is provided through this pin. h1 20 int/int o o/d interrupt request the int/int goes active when one or more of the bits in registers isr0 .. isr2 are set to ? 1 ? . a read to these registers clears the interrupt. the int/ int line is inactive when all interrupt status bits are reset. interrupt sources can be unmasked in registers imr0 .. imr2 by setting the corresponding bits to ? 0 ? . table 1 microprocessor bus interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 32 2000-09-14 h9 54 ready dtack o o ready (intel bus mode) data transfer acknowledge (motorola mode) during a slave access (register read/write) this signal (output) indicates, that the serocco-h is ready for data transfer. the signal remains active until the data strobe (ds in motorola bus mode, rd /wr in intel bus mode) and/or the chip select (cs ) go inactive. this line is tri-state when unused. a pull-up resistor to v dd3 is recommended if this function is not used. h2 19 reset i reset with this active low signal the on-chip registers and state machines are forced to reset state. during reset all pins are in a high impedance state. table 1 microprocessor bus interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 33 2000-09-14 table 2 external dma interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 a9 84 drta o dma request transmitter channel a the transmitter on a this channel requests a dma transfer by activating the drta line. the request remains active as long as the transmit fifo requires data transfers. the amount of data bytes to be transferred from the system memory to the serial channel (= byte count) must be written first to the xbcl , xbch registers. always blocks of data (n x 32 bytes + rest ; n=0,1, ? ) are transferred till the byte count is reached. drta is deactivated with the beginning of the last write cycle. a8 86 drra o dma request receiver channel a the receiver on this serial channel requests a dma transfer by activating the drra line. the request remains active as long as the receive fifo requires data transfers, thus always blocks of data are transferred. drra is deactivated immediately following the falling edge of the last read cycle. b7 85 dacka i dma acknowledge channel a a low signal on this pin informs the serocco-h that the requested dma cycle controlled via drta or drra of this channel is in progress, i.e. the dma controller has achieved bus mastership from the cpu and will start data transfer cycles (either write or read). in conjunction with a read or write operation this input serves as access enable (similar to cs ) to the respective fifos. if dacka is active, the input to pins a(7:0) and cs is ignored and the fifos are implicitly selected. if not used, a pull-up resistor to v dd is required for this pin.
peb 20525 pef 20525 pin descriptions data sheet 34 2000-09-14 d5 88 drtb gp0 o i/o dma request transmitter channel b (corresponding to channel a) general purpose pin #0 if dma support is not enabled, this pin serves as a general pupose input/output pin. after reset this pin serves as a general purpose input. a pull-up resistor to v dd3 is recommended. c7 87 drrb gp1 o i/o dma request receiver channel b (corresponding to channel a) general purpose pin #1 if dma support is not enabled, this pin serves as a general pupose input/output pin. after reset this pin serves as a general purpose input. a pull-up resistor to v dd3 is recommended. c6 89 dackb gp2 i i/o dma acknowledge channel b (corresponding to channel a) general purpose pin #2 if dma support is not enabled, this pin serves as a general pupose input/output pin. a pull-up resistor to v dd3 is recommended if this pin is not used. table 2 external dma interface pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 35 2000-09-14 table 3 serial port pins pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 f3 17 txclk a i/o transmit clock channel a the function of this pin depends on the selected clock mode and the value of bit ? toe ? ( ccr0l register, refer to table 8 "clock modes of the sccs" on page 48 ). if programmed as input ( ccr0l .toe=?0?) , either ? the transmit clock for the channel (clock mode 0a, 2a, 4, 5b, 6a), or ? a transmit strobe signal for the channel (clock mode 1) can be provided to this pin. if programmed as output ( ccr0l .toe= ? 1 ? ) , this pin supplies either ? the transmit clock from the baud rate generator (clock mode 0b, 2b, 3b, 6b, 7b), or ? the transmit clock from the dpll circuit (clock mode 3a, 7a), or ? an active-low control signal marking the programmed transmit time-slot in clock mode 5a. f2 13 rxclk a i receive clock channel a the function of this pin depends on the selected clock mode (refer to table 8 "clock modes of the sccs" on page 48 ). a signal provided on pin rxclka may supply ? the receive clock (clock mode 0, 4, 5b), or ? the receive and transmit clock (clock mode 1, 5a), or ? the clock input for the baud rate generator (clock mode 2, 3).
peb 20525 pef 20525 pin descriptions data sheet 36 2000-09-14 e3 11 cda fsca rcga osra i i i i carrier detect channel a the function of this pin depends on the selected clock mode. it can supply ? either a modem control or a general purpose input (clock modes 0, 2, 3, 6, 7). if auto-start is programmed, it functions as a receiver enable signal. ? or a receive strobe signal (clock mode 1). polarity of cda can be set to ? active low ? with bit icd in register ccr1h . additionally, an interrupt may be issued if a state transition occurs at the cda pin (programmable feature). frame sync clock channel a (cm 5a) when the scc is in the time-slot oriented clock mode 5a, this pin functions as the frame synchronization clock input. receive clock gating channel a (cm 4) in clock mode 4 this pin is used as receive clock gating signal. if no clock gating function is required, a pull-up resistor to v dd3 is recommended. octet sync receive channel a (cm 5b) (clock mode 5b) when the scc is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), received octets are aligned to this synchronization pulse input. table 3 serial port pins (cont ? d) pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 37 2000-09-14 g1 18 rtsa o request to send channel a the function of this pin depends on the settings of bits rts, frts in register ccr1h . in bus configuration, rts can be programmed to: ? go low during the actual transmission of a frame shifted by one clock period, excluding collision bits. ? go low during reception of a data frame. ? stay always high (rts disabled). e2 10 ctsa cxda tcga osta i i i i clear to send channel a a low on the ctsa input enables the transmitter. additionally, an interrupt may be issued if a state transition occurs at the ctsa pin (programmable feature). if no ?clear to send? function is required, a pull- down resistor to v ss is recommended. collision data channel a in a bus configuration, the external serial bus must be connected to the corresponding cxda pin for collision detection. a collision is detected whenever a logical ?1? is driven on the open drain txda output but a logical ?0? is detected via cxda input. transmit clock gating channel a (cm 4) in clock mode 4 these pins are used as transmit clock gating signals. if no clock gating function is required, a pull-up resistor to v dd3 is recommended. octet sync transmit channel a (cm 5b) when the scc is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), a synchronization pulse on this input pin aligns transmit octets. table 3 serial port pins (cont ? d) pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 38 2000-09-14 f4 14 txda o o/d transmit data channel a transmit data is shifted out via this pin. it can be configured as push/pull or open drain output characteristic via bit ? ods ? in register ccr1l . e1 12 rxda i receive data channel a serial data is received on this pin. a4 96 txclk b i/o transmit clock channel b (corresponding to channel a) b4 94 rxclk b i receive clock channel b (corresponding to channel a) b3 97 cdb fscb rcgb osrb i i i i carrier detect channel b frame sync clock channel b (cm 5a) receive clock gating channel b (cm 4) octet sync receive channel b (cm 5b) (corresponding to channel a) a6 90 rtsb o request to send channel b (corresponding to channel a) c1 5 ctsb cxdb tcgb ostb i i i i clear to send channel b collision data channel b transmit clock gating channel b (cm 4) octet sync transmit channel b (cm 5b) (corresponding to channel a) d4 95 txdb o o/d transmit data channel b (corresponding to channel a) table 3 serial port pins (cont ? d) pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 39 2000-09-14 b5 91 rxdb i receive data channel b (corresponding to channel a) d3 e4 8 7 xtal1 xtal2 i o crystal connection if the internal oscillator is used for clock generation (clock modes 0b, 6, 7) the external crystal has to be connected to these pins. the internal oscillator should be powered up ( gmode :oscpd = ? 0 ? ) and the signal shaper may be activated ( gmode :dshp = ? 0 ? ). moreover, xtal1 may be used as input for a common clock source to both sccs, provided by an external clock generator (oscillator). in this case the oscillator unit may be powered down and it is recommended to bypass the shaper of the internal oscillator unit by setting bit ? dshp ? to ? 1 ? . a pull-down resistor to v ss is recommended for pin xtal1 if not used. table 4 general purpose pins pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 -23 24 25 26 gp10 gp9 gp8 gp6 i/o general purpose pins these pins serve as general purpose input/output pins. table 3 serial port pins (cont ? d) pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3
peb 20525 pef 20525 pin descriptions data sheet 40 2000-09-14 table 5 test interface pins pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 b2 99 trst i jtag reset pin (internal pull-up) for proper device operation, a reset for the boundary scan controller must be supplied to this active low pin. if the boundary scan of the serocco-h is not used, this pin can be connected to v ss to keep it in reset state. c2 2 tck i jtag test clock (internal pull-up) if the boundary scan of the serocco-h is not used, this pin may remain unconnected. a2 100 tdi i jtag test data input (internal pull-up) if the boundary scan of the serocco-h is not used, this pin may remain unconnected. a1 1 tdo o jtag test data output h8 46 tms i jtag test mode select (internal pull-up) if the boundary scan of the serocco-h is not used, this pin may remain unconnected. d7 68 test1 i test input 1 when connected to v dd3 the serocco-h works in a vendor specific test mode. this pin must be connected to v ss . c9 69 test2 i test input 2 when connected to v dd3 the serocco-h works in a vendor specific test mode. this pin must be connected to v ss .
peb 20525 pef 20525 pin descriptions data sheet 41 2000-09-14 table 6 power pins pin no. symbol in (i) out (o) function p- lfbga- 80-2 p-tqfp- 100-3 a7, b1, b8, c4, c5, e7, f1, g4, g9, h6, j1 3, 15, 21, 27, 35, 40, 47, 49, 56, 62, 70, 76, 82, 92, 98 v dd3 - digital supply voltage 3.3 v 0.3 v all pins must be connected to the same voltage potential. a3, a5, b6, b9, c3, e9, f5, f6, f8, g2, h3, j8 4, 16, 22, 28, 34, 41, 48, 50, 51, 57, 63, 71, 77, 83, 93 v ss - digital ground (0 v) all pins must be connected to the same voltage potential. d1 9 v dda - analog supply voltage 3.3 v 0.3 v this pin supplies the on-chip oscillator of the serocco-h. if no separate analog power supply is available, this pin can be directly connected to v dd3 . d2 6 v ssa - analog ground (0 v) this pin supplies the ground level to the on-chip oscillator of the serocco-h. if no separate analog power supply is available, this pin can be directly connected to v ss . ---n.c.- not connected
peb 20525 pef 20525 functional overview data sheet 42 2000-09-14 3 functional overview the functional blocks of serocco-h can be divided into two major domains: ? the microprocessor interface of serocco-h provides access to on-chip registers and to the "user" portion of the receive and transmit fifos (rfifo/xfifo). optionally these fifos can be accessed by an external 4-channel dma controller. ? the serial communication controller (scc) is capable of processing bit-synchronous (hdlc/sdlc/bitsync ppp) and octet-synchronous (octet-sync ppp) as well as fully transparent data traffic. data exchange between the serial communication controller and the microprocessor interface is performed using fifos, decoupling these two domains. 3.1 block diagram figure 9 block diagram microprocessor interface jtag test interface external dma interface serial channel a decoder/ collision detection clock control dpll transmit fifo (32 byte) receive fifo (32 byte) transmit fifo (32 byte) receive fifo (32 byte) receive fifo (32 byte) transmit fifo (32 byte) transmit protocol machine receive protocol machine brg lap control serial channel b tsa 5 7 7 6 26 oscillator
peb 20525 pef 20525 functional overview data sheet 43 2000-09-14 3.2 serial communication controller (scc) 3.2.1 protocol modes overview the scc is a multi-protocol communication controller. the core logic provides different protocol modes which are listed below: hdlc modes ? hdlc transparent operation (address mode 0) ? hdlc address recognition (address mode 1, address mode 2 8/16-bit) ? full-duplex lapb/lapd operation (automode 8/16-bit) ? half-duplex sdlc-nrm operation (automode 8-bit) ? signaling system #7 (ss7) operation point-to-point protocol (ppp) modes ? bit synchronous ppp ? octet synchronous ppp extended transparent mode a detailed description of these protocol modes is given in chapter 4 , starting on page 83 . 3.2.2 scc fifos each scc provides its own transmit and receive fifos to handle internal arbitration and microcontroller latencies. 3.2.2.1 scc transmit fifo the scc transmit fifo is divided into two parts of 32 bytes each ( ? transmit pools ? ). the interface between the two parts provides synchronization between the microprocessor accesses and the protocol logic working with the serial transmit clock.
peb 20525 pef 20525 functional overview data sheet 44 2000-09-14 figure 10 scc transmit fifo a 32 bytes fifo part is accessable by the cpu/dma controller; it accepts transmit data even if the scc is in power-down condition (register ccr0h bit pu= ? 0 ? ). the only exception is a transmit data underrun (xdu) event. in case of an xdu event (e.g. after excessive bus latency), the fifo will neither accept more data nor transfer another byte to the protocol logic. this xdu blocking mechanism prevents unexpected serial data. the blocking condition must be cleared by reading the interrupt status register isr1 after the xdu interrupt was generated. thus, the xdu interrupt indication should not be masked in register imr1 . transfer of data to the 32 byte shadow part only takes place if the scc is in power-up condition and an appropriate transmit clock is provided depending on the selected clock mode. serial data transmission will start as soon as at least one byte is transferred into the shadow fifo and transmission is enabled depending on the selected clock mode (cts signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive). 3.2.2.2 scc receive fifo the scc receive fifo is divided into two parts of 32 bytes each. the interface between the two parts provides synchronization between the microprocessor accesses and the protocol logic working with the serial receive clock. 32 byte transmit pool (accessable by cpu) 32 byte shadow part (not accessable by cpu) microprocessor/dma interface transmit protocol machine
peb 20525 pef 20525 functional overview data sheet 45 2000-09-14 figure 11 scc receive fifo new receive data is announced to the cpu with an interrupt latest when the fifo fill level reaches a chosen threshold level (selected with bitfield ? rfth(1..0) ? in register ? ccr3h ? on page 153 ). default value for this threshold level is 32 bytes. if the scc receive fifo is completely filled, further incoming data is ignored and a receive data overflow condition ( ? rdo ? ) is detected. as soon as the receive fifo provides empty space, receive data is accepted again after a frame end or frame abort sequence. the automatically generated receive status byte ( rsta ) will contain an ? rdo ? indication in this case and the next incoming frame will be received in a normal way. therefore no further cpu intervention is necessary to recover the scc from an ? rdo ? condition. a "frame" with ? rdo ? status might be a mixture of a frame partly received before the ? rdo ? event occured and the rest of this frame received after the receive fifo again accepted data and the frame was still incoming. a quite arbitrary series of data or complete frames might get lost in case of an ? rdo ? event. every frame which is completely discarded because of an ? rdo ? condition generates an ? rfo ? interrupt. the scc receive fifo can be cleared by command ? rres ? in register cmdrh . note that clearing the receive fifo during operation might delete a frame end / block end indication. a frame which was already partly transferred cannot be "closed" in this case. a new frame received after receiver reset command will be appended to this "open" frame. microprocessor/dma interface receive protocol machine 32 byte receive pool (accessable by cpu) 32 byte shadow part (not accessable by cpu)
peb 20525 pef 20525 functional overview data sheet 46 2000-09-14 3.2.2.3 scc fifo access figure 12 and figure 13 illustrate byte interpretation for intel and motorola 16-bit accesses to the transmit and receive fifos. figure 12 xfifo/rfifo word access (intel mode) figure 13 xfifo/rfifo word access (motorola mode) . . . . . . . . . . . . . . . . . . byte 1 byte 2 byte 3 byte 4 byte 5 byte 32 d(7:0) d(15:8) . . . . . . . . . . . . . . . . . . byte 1 byte 2 byte 3 byte 4 byte 5 byte 32 d(7:0) d(15:8) xfifo rfifo . . . . . . . . . . . . . . . . . . byte 1 byte 2 byte 3 byte 4 byte 5 byte 32 d(7:0) d(15:8) . . . . . . . . . . . . . . . . . . byte 1 byte 2 byte 3 byte 4 byte 5 byte 32 d(7:0) d(15:8) xfifo rfifo
peb 20525 pef 20525 functional overview data sheet 47 2000-09-14 3.2.3 clocking system the serocco-h includes an internal oscillator (osc) as well as two independent baud rate generators (brg) and two digital phase locked loop (dpll) circuits. the transmit and receive clock can be generated either externally, and supplied directly via the rxclk and/or txclk pins (called external clock modes) internally, by selecting ? the internal oscillator (osc) and/or the channel specific baud rate generator (brg) ? the internal dpll, recovering the receive (and optionally transmit) clock from the receive data stream. (called internal clock modes) there are a total of 14 different clocking modes programmable via bit field ? cm ? in register ccr0l , providing a wide variety of clock generation and clock pin functions, as shown in table 8 . the transmit clock pins (txclk) may also be configured as output clock and control signals in certain clock modes if enabled via bit ? toe ? in register ccr0l . the clocking source for the dpll ? s is always the internal channel specific brg; the scaling factor (divider) of the brg can be programmed through brrl and brrh registers. there are two channel specific internal operational clocks in the scc: one operational clock (= transmit clock) for the transmitter part and one operational clock (= receive clock) for the receiver part of the protocol logic. note: the internal timers always run using the internal transmit clock. table 7 overview of clock modes clock type source generation clock mode receive clock rxclk pins externally 0, 1, 4, 5 osc, dpll, brg, internally 2, 3a, 6, 7a 3b, 7b transmit clock txclk pins, rxclk pins externally 0a, 2a, 4, 6a 1,5 osc, dpll, brg/bcr, brg internally 3a, 7a 2b, 6b 0b, 3b, 7b
peb 20525 pef 20525 functional overview data sheet 48 2000-09-14 the internal structure of each scc channel consists of a transmit protocol machine clocked with the transmit frequency f trm and a receive protocol machine clocked with the receive frequency f rec . the clocks f trm and f rec are internal clocks only and need not be identical to external clock inputs e.g. f trm and txclk input pin. the features of the different clock modes are summarized in table 8 . note: if one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (osc) should be enabled by clearing bit gmode :oscpd. this allows connection of an external crystal to pins xtal1-xtal2. the output signal of the osc can be used for one serial channel, or for both serial channels (independent baud rate generators and dplls). moreover, xtal1 alone can be used as input for an externally generated clock. the first two columns of table 8 list all possible clock modes configured via bit field ? cm ? and bit ? ssel ? in register ccr0l . for example, clock mode 6b is choosen by writing a ? 6 ? to register ccr0l .cm(2:0) and by setting bit ccr0l .ssel equal to ? 1 ? . the following 4 columns (grouped as ? clock sources ? ) specify the source of the internal clocks. columns rec and trm correspond to the domain clock frequencies f rec and f trm . the columns grouped as ? control sources ? cover additional clock mode dependent control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or table 8 clock modes of the sccs channel configuration clock sources control sources clock mode ccr0l : cm(2..0) ccr0l : ssel to brg to dpll to rec to trm cd r- strobe x- strobe frame- sync tx rx output via txclk (if ccr0l : toe = ?1?) 0a 0b 1 2a 2b 3a 3b 4 5a 5b 6a 6b 7a 7b 0 1 x 0 1 0 1 x 0 1 0 1 0 1 ? osc ? rxclk rxclk rxclk rxclk ? ? ? osc osc osc osc ? ? ? brg brg brg ? ? ? ? brg brg brg ? rxclk rxclk rxclk dpll dpll dpll brg rxclk rxclk rxclk dpll dpll dpll brg txclk brg rxclk txclk brg/16 dpll brg txclk rxclk txclk txclk brg/16 dpll brg cd cd ? cd cd cd cd ? ? ? cd cd cd cd ? ? cd ? ? ? ? rcg (tsar/ pcmrx) (tsar/ pcmrx) ? ? ? ? ? ? txclk ? ? ? ? tcg (tsax/ pcmtx) (tsax/ pcmtx) ? ? ? ? ? ? ? ? ? ? ? ? fsc ost ? ? ? ? ? ? ? ? ? ? ? ? fsc osr ? ? ? ? ? brg ? ? brg/16 dpll brg - ts-control ? ? brg/16 dpll brg
peb 20525 pef 20525 functional overview data sheet 49 2000-09-14 synchronization signals (clock mode 5). the last column describes the function of signal txclk which in some clock modes can be enabled as output signal monitoring the effective transmit clock or providing a time slot control signal (clock mode 5). the following is an example of how to read table 8 : for clock mode 6b (row ? 6b ? ) the trm clock (column ? trm ? ) is supplied by the baudrate generator (brg) output divided by 16 (source brg/16). the brg (column ? brg ? ) is derived from the internal oscillator which is supplied by pin xtal1 and xtal2. the rec clock (column ? rec ? ) is supplied by the internal dpll which itself is supplied by the baud rate generator (column ? dpll ? ) again. note: the rec clock is dpll clock divided by 16. if enabled by bit ? toe ? in register ccr0l the resulting transmit clock can be monitored via pin txclk (last column, row ? 6b ? ).
peb 20525 pef 20525 functional overview data sheet 50 2000-09-14 the clocking concept is illustrated in a block diagram manner in the following figure: additional control signals are not illustrated (please refer to the detailed clock mode descriptions below). figure 14 clock supply overview oscillator xtal1 xtal2 rxd brg 0b 6a/b 7a/b 2a/b 3a/b dpll 16:1 rxclk txclk f dpll f brg f brg/16 f rxclk f txclk f dpll f brg f rxclk f trm transmitter receiver f rec ttl or crystal f dpll f brg f brg/16 f rxclk f txclk 3a 7a 0b 3b 7b 2b 6b 1 5a 0a 2a 6a 4 5b 2a/b 3a 6a/b 7a 3b 7b 0a/b 1 5a/b 4 settings controlled by: register ccr0, bit field 'cm' selects the clock mode number register ccr0, bit 'ssel' selects the additional a/b option
peb 20525 pef 20525 functional overview data sheet 51 2000-09-14 clock modes 3.2.3.1 clock mode 0 (0a/0b) separate, externally generated receive and transmit clocks are supplied to the scc via their respective pins. the transmit clock may be directly supplied by pin txclk (clock mode 0a) or generated by the internal baud rate generator from the clock supplied at pin xtal1 (clock mode 0b). in clock mode 0b the resulting transmit clock can be driven out to pin txclk if enabled via bit ?toe? in register ccr0l . figure 15 clock mode 0a/0b configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 2 rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 or (tx clock monitor output) clock mode 0b clock mode 0a osc ctrl. ctrl. ctrl. ctrl. f brg = f osc /k k=(n+1)/2 m
peb 20525 pef 20525 functional overview data sheet 52 2000-09-14 3.2.3.2 clock mode 1 externally generated rxclk is supplied to both the receiver and transmitter. in addition, a receive strobe can be connected via cd and a transmit strobe via txclk pin. these strobe signals work on a per bit basis. this operating mode can be used in time division multiplex applications or for adjusting disparate transmit and receive data rates. note: in extended transparent mode, the above mentioned strobe signals provide byte synchronization (byte alignment). this means that the strobe signal needs to be detected once only to transmit or receive a complete byte. figure 16 clock mode 1 configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 clock mode 1 receive strobe transmit strobe rxd cd (rx strobe) txclk (tx strobe) rxclk txd v ss (enables transmit) note: in extended transparent mode the strobe signals need to be detected once only to transmit or receive a complete byte. thus byte alignment is provided in this mode. ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 53 2000-09-14 3.2.3.3 clock mode 2 (2a/2b) the brg is driven by an external clock (rxclk pin) and delivers a reference clock for the dpll which is 16 times of the resulting dpll output frequency which in turn supplies the internal receive clock. depending on the programming of register ccr0l bit ? ssel ? , the transmit clock will be either an external input clock signal provided at pin txclk in clock mode 2a or the clock delivered by the brg divided by 16 in clock mode 2b. in the latter case, the transmit clock can be driven out to pin txclk if enabled via bit ? toe ? in register ccr0l . figure 17 clock mode 2a/2b configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 (tx clock monitor output) clock mode 2b clock mode 2a brg dpll 2 brg dpll 16:1 ctrl. ctrl. ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 54 2000-09-14 3.2.3.4 clock mode 3 (3a/3b) the brg is fed with an externally generated clock via pin rxclk. depending on the value of bit ? ssel ? in register ccr0l the brg delivers either a reference clock for the dpll which is 16 times of the resulting dpll output frequency (clock mode 3a) or delivers directly the receive and transmit clock (clock mode 3b). in the first case the dpll output clock is used as receive and transmit clock. figure 18 clock mode 3a/3b configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 (tx clock monitor output) clock mode 3b clock mode 3a brg dpll (tx clock monitor output) brg ctrl. ctrl. ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 55 2000-09-14 3.2.3.5 clock mode 4 separate, externally generated receive and transmit clocks are supplied via pins rxclk and txclk. in addition separate receive and transmit clock gating signals are supplied via pins rcg and tcg . these gating signals work on a per bit basis. figure 19 clock mode 4 configuration rxclk cts, cxd, tcg cd, fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 clock mode 4 transmit clock gate signal receive clock gate signal 2 txclk tcg txd rxclk rcg rxd 1 clock delay ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 56 2000-09-14 3.2.3.6 clock mode 5a (time slot mode) this operation mode has been designed for application in time-slot oriented pcm systems. note: for correct operation nrz data coding/encoding should be used. the receive and transmit clock are common for each channel and must be supplied externally via pin rxclk. the scc receives and transmits only during fixed time-slots. either one time-slot ? of programmable width (1 ? 512 bit, via ttsa and rtsa registers), and ? of programmable location with respect to the frame synchronization signal (via pin fsc) or up to 32 time-slots ? of constant width (8 bits), and ? of programmable location with respect to the frame synchronization signal (via pin fsc) can be selected. the time-slot locations can be programmed independently for receive and transmit direction via ttsa/rtsa and pcmtx/pcmrx registers. depending on the value programmed via those registers, the receive/transmit time-slot starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame synchronization signal. figure 20 shows how to select a time-slot of programmable width and location and figure 21 shows how to select one or more time-slots of 8-bit width. if bit ? toe ? in register ccr0l is set, the selected transmit time-slot(s) is(are) indicated at an output status signal via pin txclk, which is driven to ? low ? during the active transmit window. bit ? tscm ? in register ccr1h determines whether the internal offset counters are continuously running even if no synchronization pulse is detected at fsc signal or stopping at their maximum value. in the continuous case the repetition rate of offset counter operation is 1024 transmit or receive clocks respectively. an fsc pulse detected earlier resets the counters and starts operation again. in the non-continuous case the time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an fsc pulse is detected.
peb 20525 pef 20525 functional overview data sheet 57 2000-09-14 figure 20 selecting one time-slot of programmable delay and width 70 0 ttsn tcs tcc 0 rtsn rcs rcc 0 ttsa0..3: transmit time slot assignment register rtsa0..3: receive time slot assignment register tepcm = '0': tpcm mask disabled repcm = '0': rpcm mask disabled ts delay (transmit): 1 + ttsn*8 + tcs (1...1024) ts delay (receive): 1 + rtsn*8 + rcs (1...1024) ts width (transmit): tcc (1...512 clocks) ts width (receive): rcc (1..512) fsc rxclk active time slot ttsa1 7 ttsa0 0 7 0 7 ttsa3 ttsa2 70 0 rtsa1 7 rtsa0 0 7 0 7 rtsa3 rtsa2
peb 20525 pef 20525 functional overview data sheet 58 2000-09-14 note: if time-slot 0 is to be selected, the delay has to be as long as the pcm frame itself to achieve synchronization (at least for the 2nd and subsequent pcm frames): delay = pcm frame length = 1 + xtsn*8 + xcs. xtsn and xcs have to be set appropriately. example: time-slot 0 in e1 (2.048 mbit/s) system has to be selected. pcm frame length is 256 clocks. 256 = 1+ xtsn*8 + xcs. => xtsn = 31, xcs = 7. note: in extended transparent mode the width xcc of the selected time-slot has to be n 8 bit because of character synchronization (byte alignment). in all other modes the width can be used to define windows down to a minimum length of one bit.
peb 20525 pef 20525 functional overview data sheet 59 2000-09-14 figure 21 selecting one or more time-slots of 8-bit width the common transmit and receive clock is supplied at pin rxclk and the common frame synchronisation signal at pin fsc. the "strobe signals" for active time slots are generated internally by the time slot assigner block (tsa) independent in transmit and receive direction. when the transmit and receive pcm masks are enabled, bit fields ? tcc ? and ? rcc ? are ignored because of the constant 8-bit time slot width. ts delay (transmit): 1 + ttsn*8 + tcs (1..1024) ts delay (receive): 1 + rtsn*8 + rcs (1..1024) 31 24 23 16 15 8 7 0 pcmtx0..3: transmit pcm mask register ... 1 3 1 17 ts0 ts1 ts2 ts3 ts4 ts5 ts16 ts17 8 bit repcm = '1': tpcm mask enabled 31 24 23 16 15 8 7 0 pcmrx0..3: receive pcm mask register fsc rxclk active time slot 70 0 ttsn tcs tcc 1 ttsa0..3: transmit time slot assignment register tepcm = '1': tpcm mask enabled ttsa1 7 ttsa0 0 7 0 7 ttsa3 ttsa2 pcmtx1 pcmtx0 pcmtx3 pcmtx2 rtsn rcs rcc 1 rtsa0..3: receive time slot assignment register 70 0 rtsa1 7 rtsa0 0 7 0 7 rtsa3 rtsa2 pcmrx1 pcmrx0 pcmrx3 pcmrx2
peb 20525 pef 20525 functional overview data sheet 60 2000-09-14 figure 22 clock mode 5a configuration note: the transmit time slot delay and width is programmable via bit fields ?ttsn?, ?tcs? and ?tcc? in registers ttsa0 .. ttsa3 . the receive time slot delay and width is programmable via bit fields ?rtsn?, ?rcs? and ?rcc? in registers rtsa0 .. rtsa3 . rxclk cts , cxd, tcg cd, fsc , rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 clock mode 5a time slot indicator signal time slot assigner (tsa) rxclk fsc internal tx strobe ts delay ts width txclk ts-control txd internal rx strobe ts delay ts width rxd 012 n ... 0 n 1 ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 61 2000-09-14 the following figures provide a more detailed description of the tsa internal counter operation and exceptional cases: figure 23 clock mode 5a "continuous mode" ... fsc rxclk, txclk active tim e slot load offset ocnt : ocnt := 1024 - tsdelay ocnt := 1024 ocnt := 0 load offset ocnt : ocnt := 1024 - tsdelay load duration dcnt : ocnt := n , n < tsdelay dcnt := 0 dcnt := tswidth - 1 dcnt := 0 dcnt := 255 active time slots according pcmtx/pcmrx mode tepcm/repcm = '0' mode tepcm/repcm = '1' exceptions: a) fsc pulse period > 1024: the offset counter ocnt w ill autom aically restart after 1024 clock cycles and w ill be restarted again by the late fs c pulse! b) fsc pulse period < ( tsdelay + tswidth ), i.e. fs c pulse detected w hile duration counter still active: the offset counter ocnt w ill autom aically restart, but duration counter dcnt continues operation (transmit/receive in active time slots) clock mode 5a bit tscm='0' (continuous mode) ocnt start tsdelay + 1024 clock cycles ocnt restart fsc < 1024 clock cycles fsc dcnt start tsdelay = 1 + xtsn*8 + xcs (1...1024) ocnt restart ocnt restart ocnt start
peb 20525 pef 20525 functional overview data sheet 62 2000-09-14 each frame sync pulse starts the internal offset counter with (1024 - tsdelay) whereas tsdelay is the configured value defining the start position. whenever the offset counter reaches its maximum value 1024, it triggers the duration counter to start operation. if continuous mode is selected (bit ccr1h .tscm= ? 0 ? ) the offset counter continues starting with value 0 until another frame sync puls is detected or again the maximum value 1024 is reached. once the duration counter is triggered it runs out independently from the offset counter, i.e. an active time slot period may overlap with the next frame beginning (frame sync event, refer to exception b) in figure 23 ). figure 24 clock mode 5a "non continuous mode" if non-continuous mode is selected (bit ccr1h .tscm= ? 1 ? ) the offset counter is stopped on its maximum value 1024 until another frame sync puls is detected. this allows frame sync periods greater than 1024 clock cycles, but the accesible part is limited by the range of tsdelay value (1..1024) plus tswidth (1..512) or plus 256 clock cycles if the pcm mask is selected. ocnt := tsdelay - 1 exceptions: a) fsc pulse period > 1024: the offset counter ocnt will stop on its maximum value 1024, which triggers the duration counter dcnt and will be restarted again by the 'late' fsc pulse! clock mode 5a bit tscm='1' (non continuous mode) ocnt start tsdelay + 1024 clock cycles ocnt stop ocnt start fsc a different behavior to clock mode 5a continous mode is given only in case of exception a).
peb 20525 pef 20525 functional overview data sheet 63 2000-09-14 3.2.3.7 clock mode 5b (octet sync mode) this operation mode has been designed for applications using octet synchronous ppp. it is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported, i.e. bits ttsa1 .tepcm and rtsa1 .repcm must be set to ? 1 ? . clock mode 5b provides octet alignment to time slots if octet synchronous ppp protocol mode or extended transparent mode is selected. note: for correct operation nrz data coding/encoding should be used. the receive and transmit clocks are separate and must be supplied at pins rxclk and txclk. the scc receives and transmits only during fixed octet wide time-slots of programmable location with respect to the octet synchronization signals (via pins osr and ost) the time-slot locations can be programmed independently for receive and transmit direction via registers ttsa0 .. ttsa3 / rtsa0 .. rtsa3 and pcmtx0 .. pcmtx3 / pcmrx0 .. pcmrx3 . figure 25 shows how to select one or more octet wide time-slots. bit ? tscm ? in register ccr1h determines whether the internal counters are continuously running even if no synchronization pulse is detected at ost/osr signals or stopping at their maximum value. in the continuous case the repetition rate of operation is 1024 transmit or receive clocks respectively. an ost/osr pulse detected earlier resets the corresponding offset counter and starts operation again. in the non-continuous case the transmit/receive time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an ost/ osr pulse is detected.
peb 20525 pef 20525 functional overview data sheet 64 2000-09-14 figure 25 selecting one or more octet wide time-slots the transmit and receive clocks are supplied at pins rxclk and txclk. the octet synchronisation signals are supplied at pins osr and ost. the "strobe signals" for active time slots are generated internally by the time slot assigner blocks (tsa) independent in transmit and receive direction. bit fields ? tcc ? and ? rcc ? are ignored because of the constant 8-bit time slot width. ts delay (transmit): 1 + ttsn*8 + tcs (1...1024) ts delay (receive): 1 + rtsn*8 + rcs (1...1024) ... ts0 ts1 ts2 ts3 ts4 ts5 ts16 ts17 8 bit osr ost rxclk txclk active time slot 31 24 23 16 15 8 7 0 pcmtx0..3: transmit pcm mask register 1 3 1 17 70 0 ttsn tcs tcc 1 ttsa0..3: transmit time slot assignment register tepcm = '1': tpcm mask enabled ttsa1 7 ttsa0 0 7 0 7 ttsa3 ttsa2 pcmtx1 pcmtx0 pcmtx3 pcmtx2 repcm = '1': tpcm mask enabled 31 24 23 16 15 8 7 0 pcmrx0..3: receive pcm mask register rtsn rcs rcc 1 rtsa0..3: receive time slot assignment register 70 0 rtsa1 7 rtsa0 0 7 0 7 rtsa3 rtsa2 pcmrx1 pcmrx0 pcmrx3 pcmrx2
peb 20525 pef 20525 functional overview data sheet 65 2000-09-14 figure 26 clock mode 5b configuration note: the transmit time slot delay and width is programmable via bit fields ? ttsn ? , ? tcs ? and ? tcc ? in registers ttsa0 .. ttsa3 . the receive time slot delay and width is programmable via bit fields ? rtsn ? , ? rcs ? and ? rcc ? in registers rtsa0 .. rtsa3 . rxclk cts, cxd, tcg, ost cd, fsc, rcg, osr txclk rts rxd txd xtal1 xtal2 clock supply 1 clock mode 5b time slot assigner (rtsa) rxclk txclk osr ost internal tx strobe ts delay ts width txd internal rx strobe ts delay ts width rxd 012 n ... 0 n ctrl. ctrl. time slot assigner (ttsa) 2
peb 20525 pef 20525 functional overview data sheet 66 2000-09-14 3.2.3.8 clock mode 6 (6a/6b) this clock mode is identical to clock mode 2a/2b except that the clock source of the brg is supplied at pin xtal1. the brg is driven by the internal oscillator and delivers a reference clock for the dpll which is 16 times the resulting dpll output frequency which in turn supplies the internal receive clock. depending on the programming of register ccr0l bit ? ssel ? , the transmit clock will be either an external input clock signal provided at pin txclk in clock mode 6a or the clock delivered by the brg divided by 16 in clock mode 6b. in the latter case, the transmit clock can be driven out to pin txclk if enabled via bit ? toe ? in register ccr0l . figure 27 clock mode 6a/6b configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 clock supply 1 rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 (tx clock monitor output) clock mode 6b clock mode 6a brg dpll brg dpll 16:1 or v ss v ss or osc osc ctrl. ctrl. ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 67 2000-09-14 3.2.3.9 clock mode 7 (7a/7b) this clock mode is identical to clock mode 3a/3b except that the clock source of the brg is supplied at pin xtal1. the brg is driven by the internal oscillator. depending on the value of bit ? ssel ? in register ccr0l the brg delivers either a reference clock for the dpll which is 16 times the resulting dpll output frequency (clock mode 7a) or delivers directly the receive and transmit clock (clock mode 7b). in clock mode 7a the dpll output clocks receive and transmit data. figure 28 clock mode 7a/7b configuration rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 rxclk cts , cxd, tcg cd , fsc, rcg txclk rts rxd txd xtal1 xtal2 (tx clock monitor output) clock mode 7b clock mode 7a brg dpll (tx clock monitor output) brg or v ss v ss osc osc or ctrl. ctrl. ctrl. ctrl.
peb 20525 pef 20525 functional overview data sheet 68 2000-09-14 3.2.4 baud rate generator (brg) each serial channel provides a baud rate generator (brg) whose division factor is controlled by registers brrl and brrh . whether the brg is in the clocking path or not depends on the selected clock mode. the clock division factor k is calculated by: 3.2.5 clock recovery (dpll) the scc offers the advantage of recovering the received clock from the received data by means of internal dpll circuitry, thus eliminating the need to transfer additional clock information via a separate serial clock line. for this purpose, the dpll is supplied with a ? reference clock ? from the brg which is 16 times the expected data clock rate (clock mode 2, 3a, 6, 7a). the transmit clock may be obtained by dividing the output of the brg by a constant factor of 16 (clock mode 2b, 6b; bit ? ssel ? in register ccr0l set) or also directly from the dpll (clock mode 3a, 7a). the main task of the dpll is to derive a receive clock and to adjust its phase to the incoming data stream in order to enable optimal bit sampling. the mechanism for clock recovery depends on the selected data encoding (see ? data encoding ? on page 74 ). the following functions have been implemented to facilitate a fast and reliable synchronization: table 9 brrl/brrh register and bit-fields register bit-fields offset pos. name default description brrl 38 h /88 h 5..0 brn 0 baud rate factor n range n = 0..63 brrh 39 h /89 h 11..8 brm 0 baud rate factor m, range m = 0..15 kn1 + 2 m = f brg f in k =
peb 20525 pef 20525 functional overview data sheet 69 2000-09-14 interference rejection and spike filtering two or more edges in the same directional data stream within a time period of 16 reference clocks are considered to be interference and consequently no additional clock adjustment is performed. phase adjustment (pa) referring to figure 29 , figure 30 and figure 31 , in the case where an edge appears in the data stream within the pa fields of the time window, the phase will be adjusted by 1/ 16 of the data. phase shift (ps) (nrz, nrzi only) referring to figure 29 in the case where an edge appears in the data stream within the ps field of the time window, a second sampling of the bit is forced and the phase is shifted by 180 degrees. note: edges in all other parts of the time window will be ignored. this operation facilitates a fast and reliable synchronization for most common applications. above all, it implies a very fast synchronization because of the phase shift feature: one edge on the received data stream is enough for the dpll to synchronize, thereby eliminating the need for synchronization patterns, sometimes called preambles. however, in case of extremely high jitter of the incoming data stream the reliability of the clock recovery cannot be guaranteed. the scc offers the option to disable the phase shift function for nrz and nrzi encodings by setting bit ? psd ? in register ccr0l to ? 1 ? . in this case, the pa fields are extended as shown in figure 30 . now, the dpll is more insensitive to high jitter amplitudes but needs more time to reach the optimal sampling position. to ensure correct data sampling, preambles should precede the data information. figure 29 , figure 30 and figure 31 explain the dpll algorithms used for the different data encodings.
peb 20525 pef 20525 functional overview data sheet 70 2000-09-14 figure 29 dpll algorithm (nrz and nrzi encoding, phase shift enabled) figure 30 dpll algorithm (nrz and nrzi encoding, phase shift disabled) 0123456789 10 11 12 13 14 15 0 +pa ps -pa 0 bit cell dpll count output dpll correction itd01806 0 123456789101112131415 0+pa -pa 0 bit cell dpll count output dpll correction itd04820
peb 20525 pef 20525 functional overview data sheet 71 2000-09-14 figure 31 dpll algorithm for fm0, fm1 and manchester encoding to supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the dpll. 3.2.6 scc timer operation each scc provides a general purpose timer e.g. to support protocol functions. in all operating modes the timer is clocked by the effective transmit clock. in clock mode 5 (time-slot oriented mode) the clock source for the timer can be optionally switched to the frame sync clock (input pin fsc) by setting bit ? src ? in register timr3 . the timer is controlled by the cpu via access to registers cmdrl and timr0 .. timr3 . the timer can be started any time by setting bit ? sti ? in register cmdrl . after the timer has expired it generates a timer interrupt ( ? tin ? ). with bit field ? cnt(2..0) ? in register timr3 the number of automatic timer restarts can be programmed. if the maximum value ? 111 ? is entered, a timer interrupt is generated periodically, with the time period determined by bit field ? tvalue ? (registers timr0 .. timr3 ). the timer can be stopped any time by setting bit ? tres ? in register cmdrl to ? 1 ? . in hdlc automode the timer is used internally for autonomous protocol functions (refer to the chapter ? automode ? on page 84 ). if this operating mode is selected, bit ? tmd ? in register timr3 must be set to ? 1 ? . 0 1 2 3 4 5 6 7 8 9 101112131415 0 +pa - ignore - -pa 0 bit cell (fm coding) dpll count clock transmit correction itd01807 7 6 5 4 3 2 1 0 bit cell (manchester coding) +pa - ignore - receive clock
peb 20525 pef 20525 functional overview data sheet 72 2000-09-14 3.2.7 scc serial bus configuration mode beside the point-to-point configuration, the scc effectively supports point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods. in a pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves), or in a multimaster configuration, data transmission can be initiated by each station over a common transmit line (bus). in case more than one station attempts to transmit data simultaneously (collision), the bus has to be assigned to only one station. a collision-resolution procedure is implemented in the scc. bus assignment is based on a priority mechanism with rotating priorities. this allows each station a bus access within a predetermined maximum time delay (deterministic csma/cd), no matter how many transmitters are connected to the serial bus. prerequisites for bus operation are: nrz encoding ? or ? ing of data from every transmitter on the bus (this can be realized as a wired-or, using the txd open drain capability) feedback of bus information (cxd input). the bus configuration is selected via bitfield sc(2:0) in register ccr0h . note: central clock supply for each station is not necessary if both the receive and transmit clock is recovered by the dpll (clock modes 3a, 7a). this minimizes the phase shift between the individual transmit clocks. the bus configuration mode operates independently of the clock mode, e.g. also together with clock mode 1 (receive and transmit strobe operation). 3.2.8 serial bus access procedure the idle state of the bus is identified by eight or more consecutive ? 1 ? s. when a device starts transmission of a frame, the bus is recognized to be busy by the other devices at the moment the first ? zero ? is transmitted (e.g. first ? zero ? of the opening flag in hdlc mode). after the frame has been transmitted, the bus becomes available again (idle). note: if the bus is occupied by other transmitters and/or there is no transmit request in the scc, logical ? 1 ? will be continuously transmitted on txd. 3.2.9 serial bus collisions and recovery during the transmission, the data transmitted on txd is compared with the data on cxd. in case of a mismatch ( ? 1 ? sent and ? 0 ? detected, or vice versa) data transmission is immediately aborted, and idle (logical ? 1 ? ) is transmitted.
peb 20525 pef 20525 functional overview data sheet 73 2000-09-14 hdlc/sdlc: transmission will be initiated again by the scc as soon as possible if the first part of the frame is still present in the scc transmit fifo. if not, an xmr interrupt is generated. since a ? zero ? ( ? low ? ) on the bus prevails over a ? 1 ? (high impedance) if a wired-or connection is implemented, and since the address fields of the hdlc frames sent by different stations normally differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. the frame of the transmitter with the highest temporary priority (determined by the address field) is not affected and is transmitted successfully. all other stations cease transmission immediately and return to bus monitoring state. note: if a wired-or connection has been realized by an external pull-up resistor without decoupling, the data output (txd) can be used as an open drain output and connected directly to the cxd input. for correct identification as to which frame is aborted and thus has to be repeated after an xmr interrupt has occurred, the contents of scc transmit fifo have to be unique, i.e. scc transmit fifo should not contain data of more than one frame. for this purpose new data may be provided to the transmit fifo only after ? alls ? interrupt status is detected. 3.2.10 serial bus access priority scheme to ensure that all competing stations are given a fair access to the transmission medium, a two-stage bus access priority scheme is supported by serocco-h: once a station has successfully completed the transmission of a frame, it is given a lower level of priority. this priority mechanism is based on the requirement that a station may attempt transmitting only when a determined number of consecutive ? 1 ? s are detected on the bus. normally, a transmission can start when eight consecutive ? 1 ? s on the bus are detected (through pin cxd). when an hdlc frame has been successfully transmitted, the internal priority class is decreased. thus, in order for the same station to be able to transmit another frame, ten consecutive ? 1 ? s on the bus must be detected. this guarantees that the transmission requests of other stations are satisfied before the same station is allowed a second bus access. when ten consecutive ? 1 ? s have been detected, transmission is allowed again and the priority class (of all stations) is increased (to eight ? 1 ? s). inside a priority class, the order of transmission (individual priority) is based on the hdlc address, as explained in the preceding paragraph. thus, when a collision occurs, it is always the station transmitting the only ? zero ? (i.e. all other stations transmit a ? one ? ) in a bit position of the address field that wins, all other stations cease transmission immediately.
peb 20525 pef 20525 functional overview data sheet 74 2000-09-14 3.2.11 serial bus configuration timing modes if a bus configuration has been selected, the scc provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. timing mode 1 ( ccr0h :sc(2:0) = ? 001 ? ) data is output with the rising edge of the transmit clock via the txd pin, and evaluated 1/2 a clock period later at the cxd pin with the falling clock edge. timing mode 2 ( ccr0h :sc(2:0) = ? 011 ? ) data is output with the falling clock edge and evaluated with the next falling clock edge. thus one complete clock period is available between data output and collision detection. 3.2.12 functions of signal rts in hdlc mode in clock modes 0 and 1, the rts output can be programmed via register ccr1 (soc bits) to be active when data (frame or character) is being transmitted. this signal is delayed by one clock period with respect to the data output txd, and marks all data bits that could be transmitted without collision (see figure 32 ). in this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. figure 32 request-to-send in bus operation note: for details on the functions of the rts pin refer to ?modem control signals (rts, cts, cd)? on page 77 . 3.2.13 data encoding the scc supports the following coding schemes for serial data: ? non-return-to-zero (nrz) ? non-return-to-zero-inverted (nrzi) ? fm0 (also known as bi-phase space) ? fm1 (also known as bi-phase mark) itt00242 collision txd cxd rts
peb 20525 pef 20525 functional overview data sheet 75 2000-09-14 ? manchester (also known as bi-phase) the desired line coding scheme can be selected via bit field ? sc(2:0) ? in register ccr0h . 3.2.13.1 nrz and nrzi encoding nrz: the signal level corresponds to the value of the data bit. by programming bit ? div ? ( ccr1l register), the scc may invert the transmission and reception of data. nrzi: a logical ? 0 ? is indicated by a transition and a logical ? 1 ? by no transition at the beginning of the bit cell. figure 33 nrz and nrzi data encoding 3.2.13.2 fm0 and fm1 encoding fm0: an edge occurs at the beginning of every bit cell. a logical ? 0 ? has an additional edge in the center of the bit cell, whereas a logical ? 1 ? has none. the transmit clock precedes the receive clock by 90 . fm1: an edge occurs at the beginning of every bit cell. a logical ? 1 ? has an additional edge in the center of the bit cell, a logical ? 0 ? has none. the transmit clock precedes the receive clock by 90 . 0110010 itd05313 transmit / receive clock nrz nrzi
peb 20525 pef 20525 functional overview data sheet 76 2000-09-14 figure 34 fm0 and fm1 data encoding 3.2.13.3 manchester encoding manchester: in the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. at the center of the bit cell this level is inverted. the transmit clock precedes the receive clock by 90 . the bit cell is shifted by 180 in comparison with fm coding. figure 35 manchester data encoding 110010 itd01809 receive clock fm0 fm1 transmit clock 110010 itd01810 receive clock manchester transmit clock
peb 20525 pef 20525 functional overview data sheet 77 2000-09-14 3.2.14 modem control signals (rts , cts , cd) 3.2.14.1 rts /cts handshaking the scc provides two pins (rts , cts ) per serial channel supporting the standard request-to-send modem handshaking procedure for transmission control. a transmit request will be indicated by outputting logical ? 0 ? on the request-to-send output (rts ). it is also possible to control the rts output by software. after having received the permission to transmit (cts ) the scc starts data transmission. in the case where permission to transmit is withdrawn in the course of transmission, the frame is aborted and idle is sent. after transmission is enabled again by re-activation of cts , and if the beginning of the frame is still available in the scc, the frame will be re-transmitted (self-recovery). however, if the permission to transmit is withdrawn after the data available in the shadow part of the scc transmit fifo has been completely transmitted and the pool is released, the transmitter and the scc transmit fifo are reset, the rts output is deactivated and an interrupt (xmr) is generated. note: for correct identification as to which frame is aborted and thus has to be repeated after an xmr interrupt has occurred, the contents of scc transmit fifo have to be unique, i.e. scc transmit fifo should not contain data of more than one frame, which could happen if transmission of a new frame is started by providing new data to the transmitter too early. for this purpose the ? all sent ? interrupt ( isr1 .alls) has to be waited for before providing new transmit data. note: in the case where permission to transmit is not required, the cts input can be connected directly to v ss and/or bit ? fcts ? (register ccr1h ) may be set to ? 1 ? . additionally, any transition on the cts input pin, sampled with the transmit clock, will generate an interrupt indicated via register isr1 , if this function is enabled by setting the ? csc ? bit in register imr1 to ? 0 ? .
peb 20525 pef 20525 functional overview data sheet 78 2000-09-14 figure 36 rts /cts handshaking beyond this standard rts function, signifying a transmission request of a frame (request to send), in hdlc mode the rts output may be programmed for a special function via soc1, soc0 bits in the ccr1l register. this is only available if the serial channel is operating in a bus configuration mode in clock mode 0 or 1. if soc1, soc0 bits are set to ? 11 ? , the rts output is active (= low) during the reception of a frame. if soc1, soc0 bits are set to ? 10 ? , the rts output function is disabled and the rts pin remains always high. 3.2.14.2 carrier detect (cd) receiver control similar to the rts /cts control for the transmitter, the scc supports the carrier detect modem control function for the serial receiver if the carrier detect auto start (cas) function is programmed by setting the ? cas ? bit in register ccr1h . this function is always available in clock modes 0, 2, 3, 6, 7 via the cd pin. in clock mode 1 the cd function is not supported. see table 8 for an overview. if the cas function is selected, the receiver is enabled and data reception is started when the cd input is detected to be high. if cd input is set to ? low ? , reception of the current character (byte) is still completed. 3.2.15 local loop test mode to provide fast and efficient testing, the scc can be operated in a test mode by setting the ? tlp ? bit in register ccr2l . the on-chip serial data input and output signals (txd, itt00244 sampling cts txclk txd rts ~ ~~ ~ ~ ~ ~ ~
peb 20525 pef 20525 functional overview data sheet 79 2000-09-14 rxd) are connected, generating a local loopback. as a result, the user can perform a self-test of the scc. figure 37 scc test loop transmit data can be disconnected from pin txd by setting bit tlpo in register ccr2l . note: a sufficient clock mode must be used for test loop operation such that receiver and transmitter operate with the same frequencies depending on the clock supply (e.g. clock mode 2b or 6b). 3.3 microprocessor interface the communication between the cpu and serocco-h is done via a set of directly accessible registers. the interface may be configured as intel or motorola type (refer to description of pin ? bm ? ) with a selectable data bus width of 8 or 16 bit (refer to description of pin ? width ? ). note: for the serocco-h in p-lfbga-80-2 package only an 8-bit wide bus interface is supported. the cpu transfers data to/from serocco-h (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to the lower/upper part of the data bus is determined by signals bhe / ble as shown in table 10 (intel mode) or by the upper and lower data strobe signals uds /lds as shown in table 11 (motorola mode). scc transmit logic scc receive logic tlp='0' tlp='1' rxd txd tlpo='0' tlpo='1' idle '1'
peb 20525 pef 20525 functional overview data sheet 80 2000-09-14 each of the two serial channels of serocco-h is controlled via an identical, but completely independent register set (channel a and b). global functions that are common to or independent from the two serial channels are located in global registers. 3.4 external dma controller support the serocco-h comprises a 4-channel dma interface for fast and effective data transfers using an external dma controller. for both serial channels, a separate dma request output for transmit (drt) and receive direction (drr) as well as a dma acknowledgement input (dack ) is provided. the serocco-h activates the drr/drt line as long as data transfers are needed from/to the specific fifo (level triggered demand transfer mode of dma controller). it is the responsibility of the dma controller to perform the correct amount of bus cycles. either read cycles will be performed if the dma transfer has been requested from the receiver, or write cycles if dma has been requested from the transmitter. if the dma controller provides a dma acknowledge signal (dack pin, input to the serocco-h), each bus cycle implicitly selects the top of the specific fifo and neither address (via a0..a7) nor chip select need to be supplied (i/o to memory transfers). if no dack signal is provided, normal read/write operations (providing addresses) must be performed (memory to memory transfers). the serocco-h deactivates the drr/drt line immediately after the last read/write cycle of the data transfer has started. table 10 data bus access 16-bit intel mode bhe ble register access data pins used 0 0 word access (16 bit) d(15:0) 0 1 byte access (8 bit), odd address d(15:8) 1 0 byte access (8 bit), even address d(7:0) 1 1 no data transfer - table 11 data bus access 16-bit motorola mode uds lds register access data pins used 0 0 word access (16 bit) d(15:0) 0 1 byte access (8 bit), even address d(15:8) 1 0 byte access (8 bit), odd address d(7:0) 1 1 no data transfer -
peb 20525 pef 20525 functional overview data sheet 81 2000-09-14 3.5 interrupt architecture for certain events in serocco-h an interrupt can be generated, requesting the cpu to read status information from serocco-h. the interrupt line int/int is asserted with the output characteristics programmed in bit field ? ipc(1..0) ? in register ? gmode ? on page 112 (open drain/push pull, active low/high). since only one interrupt request output is provided, the cause of an interrupt must be determined by the cpu by reading the interrupt status registers ( gstar , isr0 , isr1 , isr2 , disr , gpisl / gpish ). figure 38 interrupt status registers each interrupt indication of registers isr0 , isr1 , isr2 , disr and gpisl / gpish can be selectively unmasked by resetting the corresponding bit in the corresponding mask registers imr0 , imr1 , imr2 , dimr and gpiml / gpimh . use of these registers depends on the selected serial mode. if bit ? vis ? in register ccr0l is set to ? 1 ? , masked interrupt status bits are visible in the interrupt status registers isr0 .. isr2 . interrupts masked in registers imr0 .. imr2 will not generate an interrupt though. a read access to the interrupt status registers clears the bits. a global interrupt mask bit (bit ? gim ? in register gmode ) suppresses interrupt generation at all. to enable the interrupt system after reset, this bit must be set to ? 0 ? . gpim gpi dmi isa2 isa1 isa0 isb2 isb1 isb0 gpis imr2 (ch a) isr2 (ch a) imr1 (ch a) isr1 (ch a) imr0 (ch a) isr0 (ch a) channel a channel b gstar dimr disr
peb 20525 pef 20525 functional overview data sheet 82 2000-09-14 the global interrupt status register ( gstar ) serves as pointer to pending channel related interrupts and general purpose port interrupts. 3.6 general purpose port pins 3.6.1 gpp functional description general purpose port pins are provided on pins gp6, gp8, gp9 and gp10 in p-tqfp- 100-3 package (not provided in p-lfbga-80-2 package). if external dma support is not enabled, pins gp0...gp2 are available as general purpose pins (in both p-tqfp-100-3 and p-lfbga-80-2 package). every pin is separately programmable via the general purpose port direction registers gpdirl / gpdirh to operate as an output (bit gpndir= ? 0 ? ) or as an input (bit gpndir= ? 1 ? , reset value). if defined as output, the state of the pin is directly controlled via the general purpose port data registers gpdatl / gpdath . read access to these registers delivers the current state of all gpp pins (input and output signals). if defined as input, the state of the pin is monitored. the signal state of the corresponding gp pins is sampled with a rising edge of clk and is readable via registers gpdatl / gpdath . 3.6.2 gpp interrupt indication the gpp block generates interrupts for transitions on each input signal. all changes may be indicated via interrupt (optional). to enable interrupt generation, the corresponding interrupt mask bit in registers gpiml / gpimh must be reset to ? 0 ? . bit gpi in the gloabl interrupt status register ( gstar ) is set to ? 1 ? if an interrupt was generated by any one or more of the the general purpose port pins. the gpp pin causing the interrupt can be located by reading the gpisl / gpish registers.
peb 20525 pef 20525 detailed protocol description data sheet 83 2000-09-14 4 detailed protocol description the following table 12 provides an overview of all supported protocol modes and . the desired protocol mode is selected via bit fields in the channel configuration registers ccr2l and ccr3l . table 12 protocol mode overview all modes are discussed in details in this chapter. 4.1 hdlc/sdlc protocol modes the hdlc controller of each serial channel (scc) can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way satisfying almost any application specific requirements. there are 4 different hdlc operating modes which can be selected via register bits ccr2l :mds[1:0] and ccr2l :adm. the following table provides an overview of the different address comparison mechanisms in hdlc operating modes: protocol mode register ccr2l - bit field: ccr3l mds adm pppm ess7 hdlc automode (lap d / lap b / sdlc-nrm) 16 bit ? 00 ?? 1 ?? 00 ?? 0 ? 8 bit ? 00 ?? 0 ? hdlc address mode 2 16 bit ? 01 ?? 1 ? 8 bit ? 01 ?? 0 ? hdlc address mode 1 ? 10 ?? 1 ? hdlc address mode 0 ? 10 ?? 0 ? signaling system #7 (ss7) operation ? 10 ?? 0 ?? 00 ?? 1 ? bit synchronous ppp mode ? 10 ?? 0 ?? 11 ?? 0 ? octet synchronous ppp mode ? 01 ? extended transparent mode 1) 1) extended transparent mode is a fully bit-transparent transmission/reception mode. ? 11 ?? 1 ?? 00 ?? 0 ?
peb 20525 pef 20525 detailed protocol description data sheet 84 2000-09-14 4.1.0.1 automode characteristics: window size 1, random message length, address recognition. the scc processes autonomously all numbered frames (s-, i-frames) of an hdlc protocol. the hdlc control field, i-field data of the frames and an additional status byte are temporarily stored in the scc receive fifo. depending on the selected address mode, the scc can perform a 2-byte or 1-byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value fe h or fc h (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r), depending on the setting of the cri bit in rah1 , and will be excluded from the address comparison. similarly, two comparison values can be programmed in special registers ( ral1 , ral2 ) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the scc can be called (addressed) with 6 different address combinations, however, only the logical connection identified through the address combination rah1 / ral1 will be processed in table 13 address comparison overview mode address field recognized address bytes for a match: high address byte low address byte address mode 2 - auto mode 16 bit fe h / fc h (1111 11 c/r 0 2 ) and ral1 fe h / fc h (1111 11 c/r 0 2 ) and ral2 rah1 and ral1 rah1 and ral2 rah2 and ral1 rah2 and ral2 8 bit ral1 don ? t care ral2 don ? t care address mode 1 8 bit fe h / fc h (1111 11 c/r 0 2 ) don ? t care rah1 don ? t care rah2 don ? t care address mode 0 none don ? t care don ? t care
peb 20525 pef 20525 detailed protocol description data sheet 85 2000-09-14 the auto-mode, all others in the non auto-mode. hdlc frames with address fields that do not match any of the address combinations, are ignored by the scc. in the case of a 1-byte address, only ral1 and ral2 will be used as comparison values. according to the x.25 lapb protocol, the value in ral1 will be interpreted as command and the value in ral2 as response. the address bytes can be masked to allow selective broadcast frame recognition. for further information see ? receive address handling ? on page 88 . 4.1.0.2 address mode 2 characteristics: address recognition, arbitrary window size. all frames with valid addresses (address recognition identical to auto-mode) are forwarded directly to the rfifo. the hdlc control field, i-field data and an additional status byte are temporarily stored in the scc receive fifo. in address mode 2, all frames with a valid address are treated similarly. the address bytes can be masked to allow selective broadcast frame recognition. 4.1.0.3 address mode 1 characteristics: address recognition high byte. only the high byte of a 2-byte address field will be compared. the address byte is compared with the fixed value fe h or fc h (group address) as well as with two individually programmable values rah1 and rah2 . the whole frame excluding the first address byte will be stored in the scc receive fifo. the address bytes can be masked to allow selective broadcast frame recognition. 4.1.0.4 address mode 0 characteristics: no address recognition no address recognition is performed and each complete frame will be stored in the scc receive fifo. 4.1.1 hdlc receive data processing the following figures give an overview about the management of the received frames in the different hdlc operating modes. the graphics show the actual hdlc frame and how serocco-h interprets the incoming octets. below that it is shown which octets are stored in the rfifo and will thus be transferred into memory.
peb 20525 pef 20525 detailed protocol description data sheet 86 2000-09-14 figure 39 hdlc receive data processing in 16 bit automode figure 40 hdlc receive data processing in 8 bit automode figure 41 hdlc receive data processing in address mode 2 (16 bit) crc16 flag flag (high) (low) 16 bit addr ctrl i-field (data) /32 to rfifo rah1,2 ral1,2 option 1) option 2) rsta rsta registers involved (address compare) automode 16 bit crc16 flag flag (low) 8 bit addr ctrl i-field (data) /32 to rfifo ral1,2 opt. 1) option 2) rsta rsta registers involved (address compare) automode 8 bit crc16 flag flag (high) (low) 16 bit addr data /32 to rfifo rah1,2 ral1,2 option 1) option 2) rsta rsta registers involved (address compare) address mode 2 16 bit
peb 20525 pef 20525 detailed protocol description data sheet 87 2000-09-14 figure 42 hdlc receive data processing in address mode 2 (8 bit) figure 43 hdlc receive data processing in address mode 1 figure 44 hdlc receive data processing in address mode 0 option 1) the address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can optionally be forwarded to the rfifo (bit 'radd' in register ccr3h ) option 2) the 16 bit or 32 bit crc field can optionally be forwarded to the rfifo (bit 'rcrc' in register ccr3h ) crc16 flag flag (low) 8 bit addr data /32 to rfifo ral1,2 opt. 1) option 2) rsta rsta registers involved (address compare) address mode 2 8 bit crc16 flag flag 8 bit addr data /32 to rfifo rah1,2 opt. 1) option 2) rsta rsta registers involved (address compare) address mode 1 16 bit addr crc16 flag flag data /32 to rfifo option 2) rsta rsta registers involved address mode 0
peb 20525 pef 20525 detailed protocol description data sheet 88 2000-09-14 4.1.2 receive address handling the receive address low/high bytes (registers ral1 / rah1 and ral2 / rah2 ) can be masked on a per bit basis by setting the corresponding bits in the mask registers amral1 / amrah1 and amral2 / amrah2 . this allows extended broadcast address recognition. masked bit positions always match in comparison of the received frame address with the respective address fields in the receive address low/high registers. this feature is applicable to all hdlc protocol modes with address recognition (auto mode, address mode 2 and address mode 1). it is disabled if all bits of mask bit fields amral1 / amrah1 and amral2 / amrah2 are set to ? zero ? (which is the reset value). detection of the fixed group address fe h or fc h , if applicable to the selected operating mode, remains unchanged. as an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit address field of received frames can be pushed to the receive data buffer (first one/two bytes of the frame). this function is especially useful in conjunction with the extended broadcast address recognition. it is enabled by setting control bit ? radd ? in register ccr3h . 4.1.3 hdlc transmit data processing two different types of frames can be transmitted: ? i-frames and ? transparent frames as shown below.
peb 20525 pef 20525 detailed protocol description data sheet 89 2000-09-14 figure 45 scc transmit data flow (hdlc modes) for transmission of i-frames (selected via transmit command ? xif ? in register cmdrl ), the address and control fields are generated autonomously by the scc and the data in the corresponding transmit data buffer is entered into the information field of the frame. this is possible only if the scc is operated in automode . for (address-) transparent frames, the address and the control fields have to be entered in the transmit data buffer by software. this is possible in all operating modes and used also in auto-mode for sending u-frames. if bit ? xcrc ? in register ccr2h is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit data buffer as the last two or four bytes by software. the transmitted frame will be closed automatically only with a (closing) flag. crc16 flag flag 8 bit addr data /32 xfifo xad1 option 2) registers involved frames with automatic 8 or 16 bit address and control byte generation (automode): option 2) generation of the 16 or 32 bit crc field can optionally be disabled by setting bit 'xcrc' in register ccr2h, in which case the crc must be calculated and written into the last 2 or 4 bytes of the transmit fifo, to immediately proceed closing flag. 16 bitaddr xad2 crc16 flag flag data /32 xfifo option 2) frames without automatic address and control byte generation (address mode 2/1/0): ctrl internally generated
peb 20525 pef 20525 detailed protocol description data sheet 90 2000-09-14 note: the scc does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense according the hdlc protocol or not. 4.1.4 shared flags if the ? shared flag ? feature is enabled by setting bit ? sflg ? in register ccr1l the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one already available in the scc transmit fifo. in receive direction the scc always expects and handles ? shared flags ? . ? shared zeroes ? of consecutive flags are also supported. 4.1.5 one bit insertion similar to the zero bit insertion (bit stuffing) mechanism, as defined by the hdlc protocol, the scc offers a feature of inserting/deleting a ? one ? after seven consecutive ? zeros ? into the transmit/receive data stream, if the serial channel is operating in bus configuration mode. this method is useful if clock recovery is performed by dpll. since only nrz data encoding is supported in a bus configuration, there are possibly long sequences without edges in the receive data stream in case of successive ? 0 ? s received, and the dpll may lose synchronization. enabling the one bit insertion feature by setting bit ? oin ? in register ccr2h , it is guaranteed that at least after ? 5 consecutive ? 1 ? s a ? 0 ? will appear (bit stuffing), and after ? 7 consecutive ? 0 ? s a ? 1 ? will appear (one insertion) and thus a correct function of the dpll is ensured. note: as with the bit stuffing, the ? one insertion ? is fully transparent to the user, but it is not in accordance with the hdlc protocol, i.e. it can only be applied in proprietary systems using circuits that also implement this function, such as the peb 20542 and peb 20532. 4.1.6 preamble transmission if enabled via bit ? ept ? in register ccr2h , a programmable 8-bit pattern is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent out. the 8 bit preamble pattern can be programmed in register preamb and the repetition time in bit field ? pre ? of register ccr2h . note: zero bit insertion is disabled during preamble transmission. 4.1.7 crc generation and checking in hdlc/sdlc mode, error protection is done by crc generation and checking.
peb 20525 pef 20525 detailed protocol description data sheet 91 2000-09-14 in standard applications, crc-ccitt algorithm is used. the frame check sequence at the end of each frame consists of two bytes of crc checksum. if required, the crc-ccitt algorithm can be replaced by the crc-32 algorithm, enabled via bit ? c32 ? in register ccr1l . in this case the frame check sequence consists of four bytes. optionally the internal handling of received and transmitted crc checksum can be influenced via control bits ? rcrc ? , ? drcrc ? in register ccr3h and ? xcrc ? in register ccr2h . receive direction: if not disabled by setting bit ? drcrc ? (register ccr3h ), the received crc checksum is always assumed to be in the 2 (crc-ccitt) or 4 (crc-32) last bytes of a frame, immediately preceding a closing flag. if bit ? rcrc ? is set, the received crc checksum is treated as data and will be forwarded to the rfifo, where it precedes the frame status byte. nevertheless the received crc checksum is additionally checked for correctness. if crc checking is disabled with bit ccr3h :drcrc, the limits for ? valid frame ? check are modified accordingly (refer to description of the receive status byte, rsta :vfr). transmit direction: if bit ? xcrc ? is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit data buffer by software. the transmitted frame will only be closed automatically with a (closing) flag. note: the scc does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense or not according the hdlc protocol. 4.1.8 receive length check feature the scc offers the possibility to supervise the maximum length of received frames and to terminate data reception in the case that this length is exceeded. this feature is controlled via the special receive length check registers rlcrl / rlcrh . the function is enabled by setting bit ? rce ? (receive length check enable) and the maximum frame length to be checked is programmed via bit field ? rl ? . the maximum receive length can be determined as a multiple of 32-byte blocks as follows: max_length = (rl + 1) 32 , where rl is the value written to bit field ? rl ? . thus, the maximum length of receive frames can be programmed between 32 and 65536 bytes. all frames exceeding this length are treated as if they had been aborted by the remote station, i.e. the cpu is informed via ? an ? rme ? interrupt generated by the scc, and ? the receive abort indication ? rab ? in the receive status byte ( rsta ).
peb 20525 pef 20525 detailed protocol description data sheet 92 2000-09-14 additionally an optional ? flex ? interrupt is generated prior to ? rme ? , indicating that the maximum receive frame length was exceeded. receive operation continues with the beginning of the next receive frame. 4.2 point-to-point protocol (ppp) modes ppp (as described in rfc1662) can work over 3 modes: asynchronous hdlc, synchronous hdlc, and octet synchronous. the serocco-h supports bit and octet synchronous hdlc ppp for use over dial-up connections. the octet synchronous mode of ppp protocol (rfc 1662) supports ppp over sonet applications. the synchronous hdlc ppp modes are submodes of the hdlc mode. the appropriate ppp mode is selected via bit field ? pppm ? in register ccr2l . the ppp-support hardware allows software to perform segmentation and reassembly of ppp payloads, and allows serocco-h to perform the synchronous hdlc ppp protocol conversions as required for the network interface. 4.2.1 bit synchronous ppp the serocco-h transmits a data block, inserts hdlc header (opening flag), and appends the hdlc trailer (crc, ending flag). zero-bit stuffing algorithm is also performed. no character mapping is performed. the bit-synchronous ppp mode differs from the hdlc mode (address mode 0) only in the abort sequence: hdlc requires at least 7 consecutive ? 1 ? bits as abort sequence, whereas ppp requires at least 15 ? 1 ? bits. for receive operation serocco-h monitors the incoming data stream for the opening flag (7e hex) to identify the beginning of a hdlc packet. subsequent bytes are part of data and are processed as normal hdlc packet including checking of crc. 4.2.2 octet synchronous ppp the serocco-h transmits a data block, inserts hdlc header (opening flag), and appends the hdlc trailer (crc, ending flag). beside this standard hdlc operation, zero-bit stuffing is not performed, but character mapping is performed. for receive operation serocco-h monitors the incoming data stream for the opening flag (7e hex) to identify the beginning of a hdlc packet. subsequent bytes are part of data and are processed as normal hdlc packet including checking of crc. received mapped characters are unmapped. the abort sequence consists of the control escape character 7d h followed by a flag character 7e h (not stuffed). between two frames, the interframe time fill character should be programmed to 7e h by setting bit ccr2h :itf to ? 1 ? . octet alignment is provided through the synchronization pulses in clock mode 5b.
peb 20525 pef 20525 detailed protocol description data sheet 93 2000-09-14 4.2.3 data transparency in ppp mode when transporting bit-files (as opposed to text files), or compressed files, the characters could easily represent modem control characters (such as ctrl-q, ctrl-s) which the modem would not pass through. serocco-h maintains an async control character map (accm) for characters 00-1f hex. whenever there is a mapped character in the data stream, the transmitter precedes that character with a control-escape character of 7d h . after the control-escape, the character itself is transmitted with bit 5 inverted. character e.g. 13 h is mapped to 7d h , 33 h ). at the receive end, a 7d h character is discarded and the following character is modified by inverting bit 5 (e.g. if 7d h , 33 h is received, the 7d h is discarded and the 33 h is changed to 13 h the original character). this character is received into rfifo and included in crc calculation, even if it is not mapped. the 32 lookup octet values (00 h -1f h ) are stored within the on-chip registers accm0 ..3. in addition to the accm, 4 user programmable characters (especially outside the range 00-1f hex) can also be mapped using the control-escape sequence described above. these characters are specified in registers udac0 ..3. the receiver discards all characters which are received unmapped, but expected to be mapped because of accm0 ..3 and udac0 ..3 register contents. if this occurs within an hdlc frame, the unexpected characters are discarded before forwarded to the receive crc checking unit. 7d h (control-escape) and 7e h (flag) octets in the data stream are mapped in general. the sequence of mapping control logic is: 1. 7d h and 7e h octets, 2. accm0 ..3, 3. udac0 ..3. this mechanism is applied to octet synchronous hdlc ppp mode.
peb 20525 pef 20525 detailed protocol description data sheet 94 2000-09-14 figure 46 ppp mapping/unmapping example accm0..3: async control character map register 1f 0 00 0 3 1 13 1e 0 15 0 14 0 ... ... ... ... 12 0 11 0 udac0..3: user defined async control character map register 7eh 7eh 7eh 20h 13 h 20 h 01 h 02 h data in transmit fifo: hdlc framing: 13 h 20 h 01 h 02 h 7e h 7e h 33 h 00 h 01 h 02 h 7e h 7d h 7d h 7e h ppp mapping: 33 h 00 h 01 h 02 h 7e h 7d h 7d h 7e h received character: 13 h 20 h 01 h 02 h 7e h 7e h ppp unmapping : 13 h 20 h 01 h 02 h data in receive fifo: serial line note: crc generation/checking is assumed to be disabled in this example; according the ppp mapping/ unmapping, crc characters are treated as 'data' characters being mapped/unmapped if necessary . udac1 udac0 udac3 udac2 70 070 7 0 7 accm1 accm0 accm3 accm2 70 070 707
peb 20525 pef 20525 detailed protocol description data sheet 95 2000-09-14 4.3 extended transparent mode characteristics: fully transparent when programmed in the extended transparent mode via the ccr2l register (bits mds1, mds0, adm = ? 111 ? ), the scc performs fully transparent data transmission and reception without hdlc framing, i.e. without flag insertion and deletion crc generation and checking bit stuffing. this feature can be profitably used e.g. for: user specific protocol variations line state monitoring, or test purposes, in particular for monitoring or intentionally generating hdlc protocol rule violations (e.g. wrong crc) character or octet boundary synchronization can be achieved by using clock mode 5 or clock mode 1 with an external receive strobe input to pin cd. note: data is transmitted and received with the least significant bit (lsb) first. 4.4 procedural support (layer-2 functions) when operating in the auto mode, the scc offers a high degree of protocol support. in addition to address recognition, the scc autonomously processes all (numbered) s- and i-frames (window size 1 only) with either normal or extended control field format (modulo-8 or modulo-128 sequence numbers ? selectable via register ccr2h bit ? mcs ? ). the following functions will be performed: ? updating of transmit and receive counter ? evaluation of transmit and receive counter ? processing of s commands ? flow control with rr/rnr ? generation of responses ? recognition of protocol errors ? transmission of s commands, if acknowledgement is not received ? continuous status query of remote station after rnr has been received ? programmable timer/repeater functions. in addition, all unnumbered frames are forwarded directly to the processor. the logical link can be initialized by software at any time (reset hdlc receiver by rres command in register cmdrh ). additional logical connections can be operated in parallel by software.
peb 20525 pef 20525 detailed protocol description data sheet 96 2000-09-14 4.4.1 full-duplex lapb/lapd operation initially (i.e. after reset), the lap controllers of the two serial channels are configured to function as a combined (primary/secondary) station, where they autonomously perform a subset of the balanced x.25 lapb/isdn lapd protocol. reception of frames: the logical processing of received s-frames is performed by the scc without interrupting the host. the host is merely informed by interrupt of status changes in the remote station (receiver ready / receiver not ready) and protocol errors (unacceptable n(r), or s-frame with i-field). i-frames are also processed autonomously and checked for protocol errors. the i-frame will not be accepted in the case of sequence errors (no interrupt is forwarded to the host), but is immediately confirmed by an s-response. if the host sets the scc into a ? receive not ready ? status, an i-frame will not be accepted (no interrupt) and an rnr response is transmitted. u-frames are always stored in the rfifo and forwarded directly to the host. the logical sequence and the reception of a frame in auto mode is illustrated in figure 47 . note: the state variables n(s), n(r) are evaluated within the window size 1, i.e. the scc checks only the least significant bit of the receive and transmit counter regardless of the selected modulo count.
peb 20525 pef 20525 detailed protocol description data sheet 97 2000-09-14 figure 47 processing of received frames in auto mode itd00230 command with p=1 ? y ? ready rec. n f=p trm rr activ rec. set rrnr response pce int : 1 response trm rnr f=p ? overflow data n : int rme set rdo response trm rr f=p rme int : n y y n =v y n(s) (r)+1 rec. ready : int rme n set rdo data overflow ? n y alls int : acknowledge reset wait for +1 (s) = y =v n(r) (s)+1 y ? acknowledge wait for n y : int xmr reset wait for acknowledge acknowledge reset wait for alls int : response f=1 ? n (s)+1 n(r)=v n y wait for acknowledge ? n n y ? crc error set crce n n set rab aborted ? y u frame 1 y prot. error ? n pce int : : int rme set crce n ? crc error y set rab aborted ? n y i frame n 1 y prot. error ? n or abort crc error y rnr ? 1 reset rrnr ? , y crc error or abort n ? prot. error y n : int pce srej rej rr , 1 y (r)+1 (r) =v v v (s) v v (s) v= (s) +1 y ? ? alls : int ? ?
peb 20525 pef 20525 detailed protocol description data sheet 98 2000-09-14 transmission of frames: the scc autonomously transmits s commands and s responses in the auto mode. either transparent or i-frames can be transmitted by the user. the software timer has to be operated in the internal timer mode to transmit i-frames. after the frame has been transmitted, the timer is self-started, the xfifo is inhibited, and the scc waits for the arrival of a positive acknowledgement. this acknowledgement can be provided by means of an s- or i-frame. if no positive acknowledgement is received during time t 1 , the scc transmits an s- command (p = ? 1 ? ), which must be answered by an s-response (f = ? 1 ? ). if the s-response is not received, the process is performed n1 times (in hdlc known as n2, refer to register timr3 ). upon the arrival of an acknowledgement or after the completion of this poll procedure the xfifo is enabled and an interrupt is generated. interrupts may be triggered by the following: message has been positively acknowledged (alls interrupt) message must be repeated (xmr interrupt) response has not been received (tin interrupt). in automode, only when the alls interrupt has been issued data of a new frame may be provided to the xfifo! upon arrival of an rnr frame, the software timer is started and the status of the remote station is polled periodically after expiration of t 1 , until the status ? receive ready ? has been detected. the user is informed via the appropriate interrupt. if no response is received after n1 times, a tin interrupt, and t 1 clock periods thereafter an alls interrupt is generated and the process is terminated. note: the internal timer mode should only be used in the auto mode. transparent frames can be transmitted in all operating modes.
peb 20525 pef 20525 detailed protocol description data sheet 99 2000-09-14 figure 48 timer procedure/poll cycle itd00231 wait for acknowledge set ? ? 2 ? with f=1 response wait for acknowledge ? rrnr n nn y y n 2 y y = ? (r) (s)+1 v n y n 1 t load rec.rnr rec.rr i rec. frame t proc. activ tin int : 1 load t 1 y ? ready rec. n command p=1 trm rr , , trm rnr command p=1 n1 n1-1 = n ? y y ? n n1 = 7 n1 = 0 run out 1 2 2 load t 1 trm rr/rnr cmdr ; sti command p=1 trm i frame acknowledge set wait for inactiv t proc. 1 rnr set rrnr rec. 1 t load n 1 load n 1 11.06.1996 b/r
peb 20525 pef 20525 detailed protocol description data sheet 100 2000-09-14 examples the interaction between scc and the host during transmission and reception of i-frames is illustrated in the following two figures. the flow control with rr/rnr of i-frames during transmission/reception is illustrated in figure 49 . both, the sequence of the poll cycle and protocol errors are shown in figure 50 . figure 49 transmission/reception of i-frames and flow control figure 50 flow control: reception of s-commands and protocol errors rme rme wfa transmit with frame i confirm i frame alls alls wfa reception frame i transmit frame i rr(1) (0.0) i rr(1) i (0.1) (1.1) i (1.2) i rr(2) rr(0)f=1 rnr rsc (rnr) rsc (rr) xmr wfa t1 t1 rr(0)p=1 rnr(0)f=1 rnr(0) i (0.0) rr(0)p=1 alls wfa = wait for acknowledge (see status register) rnr rme xrnr rnr(0) rr (0.0) i rr(0)p=1 rr(0)f=1 rr(0)p=1 rr(0)f=1 i (0.0) rr(1) t1 t1 t1 rrp=1 poll cycle protocol error i rr(0)p=1 rr(1) rr(2) alls pce tin wfa alls rr(0) wfa rrp=1 (0.0) wfa = wait for acknowledge (see status register)
peb 20525 pef 20525 detailed protocol description data sheet 101 2000-09-14 protocol error handling: depending on the error type, erroneous frames are handled according to table 14 . note: the station variables ( v(s), v(r) ) are not changed. 4.4.2 half-duplex sdlc-nrm operation the lap controllers of the two serial channels can be configured to function in a half- duplex normal response mode (nrm), where they operate as a slave (secondary) station, by setting the nrm bit in the ccr2l register of the corresponding channel. in contrast to the full-duplex lap b/lap d operation, where the combined (primary + secondary) station transmits both commands and responses and may transmit data at any time, the nrm mode allows only responses to be transmitted and the secondary station may transmit only when instructed to do so by the master (primary) station. the scc gets the permission to transmit from the primary station via an s-, or i- frame with the poll bit (p) set . the nrm mode can be profitably used in a point-to-multipoint configuration with a fixed master-slave relationship, which guarantees the absence of collisions on the common transmit line. it is the responsibility of the master station to poll the slaves periodically and to handle error situations. prerequisite for nrm operation is: ? auto mode with 8-bit address field selected register ccr2l bit fields ? mds1 ? , ? mds0 ? , ? adm ? = ? 000 ? ? register timr3 bit ? tmd ? = ? 0 ? ? same transmit and receive addresses, since only responses can be transmitted, i.e. register xad1 = xad2 and register ral1 = ral2 (address of secondary). table 14 error handling frame type error type generated response generated interrupt rec. status i crc error aborted unexpected n(s) unexpected n(r) ? ? s-frame ? rme rme ? pce crc error abort ? ? s crc error aborted unexpected n(r) with i-field ? ? ? ? ? ? pce pce ? ? ? ?
peb 20525 pef 20525 detailed protocol description data sheet 102 2000-09-14 note: the broadcast address may be programmed in register ral2 if broadcasting is required. in this case registers ral1 and ral2 are not equal. the primary station has to operate in transparent hdlc mode. reception of frames: the reception of frames functions similarly to the lapb/lapd operation (see ? full- duplex lapb/lapd operation ? on page 96 ). transmission of frames: the scc does not transmit s-, or i-frames if not instructed to do so by the primary station via an s-, or i-frame with the poll bit set. the scc can be told to send an i-frame issuing the transmit command ? xif ? in register cmdrl . the transmission of the frame, however, will not be initiated by the scc until reception of either an rr, or i-frame with poll bit set (p = ? 1 ? ). after the frame has been transmitted (with the final bit set), the host has to wait for an alls or xmr interrupt. a secondary does not poll the primary for acknowledgements, thus timer supervision must be done by the primary station. upon the arrival of an acknowledgement the scc transmit fifo is enabled and an interrupt is forwarded to the host, either the ? message has been positively acknowledged (alls interrupt), or the ? message must be repeated (xmr interrupt). additionally, the on-chip timer can be used under host control to provide timer recovery of the secondary if no acknowledgements are received at all. note: a secondary will transmit transparent frames only if the permission to send is given by receiving an s-frame or i-frame with poll bit set (p = ? 1 ? ). examples: a few examples of scc/host interaction in the case of normal response mode (nrm) mode are shown in figure 51 and figure 52 .
peb 20525 pef 20525 detailed protocol description data sheet 103 2000-09-14 figure 51 no data to send: data reception/transmission figure 52 data transmission (without error), data transmission (with error) 4.4.3 signaling system #7 (ss7) operation the serocco-h supports the signaling system #7 (ss7) which is described in itu- q.703. ss7 support must be activated by setting bit ? ess7 ? in register ccr3l . rr(0)f=1 rr(0)p=1 secondary primary itd01800 (0,1)f=1 (0,0)p=1 itd00237 (1,1)p=1 rr(2)f=1 alls rme xif i i i (0,0)f=1 rr(0)p=1 itd00238 rr(1)p=0 alls xif i (0,0)f=1 rr(0)p=1 itd01801 rr(0)p=1 xmr xif i rr(0)f=1 t
peb 20525 pef 20525 detailed protocol description data sheet 104 2000-09-14 receive the ss7 protocol is supported by the following hardware features in receive direction: recognition of signaling unit type discard of repeatedly received fisus and optionally of lssus if content is unchanged check if the length of the received signaling unit is at least six octets (including the opening flag) check if the signal information field of a received signaling unit consists of more than 272 octets (enabled with bit ccr3l .elc). in this case, reception of the current signaling unit will be aborted. counting and processing of errored signaling units in order to reduce the microprocessor load, fill in signaling units (fisus) are processed automatically. by examining the length indicator of a received signal unit (su) serocco-h decides whether a fisu has been received. consecutively received fisus will be compared and not stored in the rfifo, if the content is equal to the previous one. the same applies to link status signaling units (lssus), if enabled with bit ccr3l .csf. the different types of signaling units as message signaling unit (msu), link status signaling unit (lssu) and fill-in signaling units (fisu) are indicated in the rsta byte (bit field ? su ? ), which is automatically added to the rfifo with each received signaling unit. the complete signaling unit except start and end flags is stored in the receive fifo. the functions of bits ccr3h .rcrc and ccr3h .radd are also valid in ss7 mode, with bit ? radd ? related to bsn (backward sequence number) and fsn (forward sequence number). errored signaling units are counted and processed according to itu-t q.703. the su counter and errored-su counter are reset by setting cmdrh .rsuc to ? 1 ? . the error threshold can be selected to be 64 (default) or 32 by clearing/setting bit ccr3l .suet. if the defined error limit is exceeded, an interrupt ( isr1 .suex) is generated, if not masked by bit imr1 .suex. transmit in transmit direction, following features are supported: single or repetitive transmission of signaling units automatic generation of fill-in signaling units (fisu) each signaling unit (su) written to the transmit fifo (xfifo) will be sent once or repeatedly including flags, crc checksum and stuffed bits. after e.g. an msu has been transmitted completely, serocco-h optionally starts sending of fill in signaling units (fisus) containing the forward sequence number (fsn) and the backward sequence number (bsn) of the previously transmitted signaling unit. setting bit ccr3l .afx to ? 1 ? causes fisus to be sent continuously if no signaling unit is to be transmitted from xfifo. after a new signaling unit has been written to the xfifo and a transmission has been initiated, the current fisu is completed and the new su is sent. after this,
peb 20525 pef 20525 detailed protocol description data sheet 105 2000-09-14 transmission of fisus continues. the internally generated fisus contain fsn and bsn of the last transmitted signaling unit written to xfifo. using cmdrl .xrep= ? 1 ? , the contents of xfifo (1..32 bytes) can be sent continuously. this cyclic transmission can be stopped with the cmdrl .xres command.
peb 20525 pef 20525 register description data sheet 106 2000-09-14 5 register description 5.1 register overview the serocco-h global registers are used to configure and control the serial communication controllers (sccs), general purpose pins (gpp) and dma operation. all registers are 8-bit organized registers, but grouped and optimized for 16 bit access. 16 bit access (p-tqfp-100-3 package) is supported to even addresses only. table 15 provides an overview about all on-chip registers: table 15 register overview offset ch register res val meaning page a b read write global registers: 00 h gcmdr 00 h global command register 111 01 h gmode 0b h global mode register 112 02 h reserved 03 h gstar 00 h global status register 114 04 h gpdirl 07 h gpp direction register (low byte) 116 05 h gpdirh ff h gpp direction register (high byte) 116 06 h gpdatl - gpp data register (low byte) 118 07 h gpdath - gpp data register (high byte) 118 08 h gpiml 07 h gpp interrupt mask register (low byte) 120 09 h gpimh ff h gpp interrupt mask register (high byte) 120 0a h gpisl 00 h gpp interrupt status register (low byte) 122 0b h gpish 00 h gpp interrupt status register (high byte) 122 0c h dcmdr 00 h dma command register 124 0d h reserved 0e h disr 00 h dma interrupt status register 125 0f h dimr 77 h dma interrupt mask register 127 channel specific registers: 10 h 60 h rfifo xfifo - receive/transmit fifo (low byte) 128 11 h 61 h - receive/transmit fifo (high byte) 128
peb 20525 pef 20525 register description data sheet 107 2000-09-14 12 h 62 h starl 00 h status register (low byte) 131 13 h 63 h starh 10 h status register (high byte) 131 14 h 64 h cmdrl 00 h command register (low byte) 135 15 h 65 h cmdrh 00 h command register (high byte) 135 16 h 66 h ccr0l 00 h channel configuration register 0 (low byte) 139 17 h 67 h ccr0h 00 h channel configuration register 0 (high byte) 139 18 h 68 h ccr1l 00 h channel configuration register 1 (low byte) 143 19 h 69 h ccr1h 00 h channel configuration register 1 (high byte) 143 1a h 6a h ccr2l 00 h channel configuration register 2 (low byte) 148 1b h 6b h ccr2h 00 h channel configuration register 2 (high byte) 148 1c h 6c h ccr3l 00 h channel configuration register 3 (low byte) 153 1d h 6d h ccr3h 00 h channel configuration register 3 (high byte) 153 1e h 6e h preamb 00 h preamble register 157 1f h 6f h reserved 20 h 70 h accm0 00 h ppp async control character map 0 158 21 h 71 h accm1 00 h ppp async control character map 1 158 22 h 72 h accm2 00 h ppp async control character map2 159 23 h 73 h accm3 00 h ppp async control character map 3 159 24 h 74 h udac0 7e h user defined ppp async control character map 0 161 25 h 75 h udac1 7e h user defined ppp async control character map 1 161 26 h 76 h udac2 7e h user defined ppp async control character map 2 162 table 15 register overview (cont ? d) offset ch register res val meaning page a b read write
peb 20525 pef 20525 register description data sheet 108 2000-09-14 27 h 77 h udac3 7e h user defined ppp async control character map 3 162 28 h 78 h ttsa0 00 h transmit time slot assignment register 0 164 29 h 79 h ttsa1 00 h transmit time slot assignment register 1 164 2a h 7a h ttsa2 00 h transmit time slot assignment register 2 165 2b h 7b h ttsa3 00 h transmit time slot assignment register 3 165 2c h 7c h rtsa0 00 h receive time slot assignment register 0 167 2d h 7d h rtsa1 00 h receive time slot assignment register 1 167 2e h 7e h rtsa2 00 h receive time slot assignment register 2 168 2f h 7f h rtsa3 00 h receive time slot assignment register 3 168 30 h 80 h pcmtx0 00 h pcm mask transmit direction register 0 170 31 h 81 h pcmtx1 00 h pcm mask transmit direction register 1 170 32 h 82 h pcmtx2 00 h pcm mask transmit direction register 2 171 33 h 83 h pcmtx3 00 h pcm mask transmit direction register 3 171 34 h 84 h pcmrx0 00 h pcm mask receive direction register 0 173 35 h 85 h pcmrx1 00 h pcm mask receive direction register 1 173 36 h 86 h pcmrx2 00 h pcm mask receive direction register 2 174 37 h 87 h pcmrx3 00 h pcm mask receive direction register 3 174 38 h 88 h brrl 00 h baud rate register (low byte) 176 39 h 89 h brrh 00 h baud rate register (high byte) 176 3a h 8a h timr0 00 h timer register 0 178 3b h 8b h timr1 00 h timer register 1 178 3c h 8c h timr2 00 h timer register 2 179 3d h 8d h timr3 00 h timer register 3 179 3e h 8e h xad1 00 h transmit address 1 register 182 3f h 8f h xad2 00 h transmit address 2 register 182 40 h 90 h ral1 00 h receive address 1 low register 184 41 h 91 h rah1 00 h receive address 1 high register 184 42 h 92 h ral2 00 h receive address 2 low register 185 43 h 93 h rah2 00 h receive address 2 high register 185 table 15 register overview (cont ? d) offset ch register res val meaning page a b read write
peb 20525 pef 20525 register description data sheet 109 2000-09-14 44 h 94 h amral1 00 h mask receive address 1 low register 187 45 h 95 h amrah1 00 h mask receive address 1 high register 187 46 h 95 h amral2 00 h mask receive address 2 low register 188 47 h 96 h amrah2 00 h mask receive address 2 high register 188 48 h 98 h rlcrl 00 h receive length check register (low byte) 190 49 h 99 h rlcrh 00 h receive length check register (high byte) 190 4a h 9a h ... reserved 4f h 9f h 50 h a0 h isr0 00 h interrupt status register 0 192 51 h a1 h isr1 00 h interrupt status register 1 192 52 h a2 h isr2 00 h interrupt status register 2 193 53 h a3 h reserved 54 h a4 h imr0 ff h interrupt mask register 0 198 55 h a5 h imr1 ff h interrupt mask register 1 198 56 h a6 h imr2 03 h interrupt mask register 2 199 57 h a7 h reserved 58 h a8 h rsta 00 h receive status byte 201 59 h a9 h ... reserved 5f h af h channel specific dma registers: b0 h ca h ... reserved b7 h d1 h b8 h d2 h xbcl 00 h transmit byte count (low byte) 206 b9 h d3 h xbch 00 h transmit byte count (high byte) 206 table 15 register overview (cont ? d) offset ch register res val meaning page a b read write
peb 20525 pef 20525 register description data sheet 110 2000-09-14 ba h d4 h ... reserved c3 h dd h c4 h de h rmbsl 00 h receive maximum buffer size (low byte) 208 c5 h df h rmbsh 00 h receive maximum buffer size (high byte) 208 c6 h e0 h rbcl 00 h receive byte count (low byte) 210 c7 h e1 h rbch 00 h receive byte count (high byte) 210 c8 h e2 h reserved c9 h e3 h reserved miscellaneous: e4 h ... reserved eb h ec h ver0 03 h version register 0 212 ed h ver1 f0 h version register 1 212 ee h ver2 05 h version register 2 213 ef h ver3 20 h version register 3 213 table 15 register overview (cont ? d) offset ch register res val meaning page a b read write
peb 20525 pef 20525 register description data sheet 111 2000-09-14 5.2 detailed register description 5.2.1 global registers each register description is organized in three parts: a head with general information about reset value, access type (read/write), offset address and usual handling; a table containing the bit information (name of bit positions); a section containing the detailed description of each bit. register 1 gcmdr global command register cpu accessibility: read/write reset value: 00 h offset address: 00 h typical usage: written by cpu, evaluated by serocco-h bit76543210 global command bits 0000000swr swr software reset command self clearing command bit: bit= ? 0 ? no software reset command is issued. bit= ? 1 ? causes serocco-h to perform a complete reset identical to hardware reset.
peb 20525 pef 20525 register description (gmode) data sheet 5-112 2000-09-14 register 2 gmode global mode register cpu accessibility: read/write reset value: 0b h offset address: 01 h typical usage: written by cpu evaluated by serocco-h bit76543210 dma and global control 0 edma ipc(1:0) oscpd 0 dshp gim edma enable external dma support this bit field controls the dma operation mode: edma= ? 0 ? the external dma controller support functions are disabled. serocco-h is operated in standard register access controlled mode. edma= ? 1 ? external dma controller support functions are enabled. ipc(1:0) interrupt pin characteristic these bits control the characteristic of interrupt output pin int/int : ipc(1:0) output function: ? 00 ? open drain active low ? 01 ? push/pull active low ? 10 ? reserved . ? 11 ? push/pull active high
peb 20525 pef 20525 register description (gmode) data sheet 5-113 2000-09-14 oscpd oscillator power down setting this bit to ? 0 ? enables the internal oscillator. for power saving purposes (escpecially if clock modes are used which do not need the internal oscillator) this bit may remain set to ? 1 ? . oscpd= ? 0 ? the internal oscillator is active. oscpd= ? 1 ? the internal oscillator is in power down mode. note: after reset this bit is set to ? 1 ? , i.e. the oscillator is in power down mode! dshp disable shaper this bit has to be set to ? 0 ? if the shaping function in the oscillator unit is desired. the shaper amplifies the oscillator signal and improves the slope of the clock edges. dshp= ? 0 ? shaper is enabled. recommended setting if a crystal is connected to pins xtal1/xtal2. dshp= ? 1 ? shaper is disabled (bypassed). recommended setting if - a ttl level clock signal is supplied to pin xtal1 - the oscillator unit is unused note: after reset this bit is set to ? 1 ? , i.e. the shaper is disabled! gim global interrupt mask this bits disables all interrupt indications via pin int/int . internal operation (interrupt generation, interrupt status register update,...) is not affected. if set, pin int/int immediately changes or remains in inactive state. gim= ? 0 ? global interrupt mask is cleared. pin int/int is controlled by the internal interrupt control logic and activated as long as at least one unmasked interrupt indication is pending (not yet confirmed by read access to corresponding interrupt status register). gim= ? 1 ? global interrupt mask is set. pin int/int remains inactive. note: after reset this bit is set to ? 1 ? , i.e. all interrupts are disabled!
peb 20525 pef 20525 register description (gstar) data sheet 5-114 2000-09-14 register 3 gstar global status register cpu accessibility: read only reset value: 00 h offset address: 03 h typical usage: written by serocco-h evaluated by cpu bit76543210 global interrupt status information gpi dmi isa2 isa1 isa0 isb2 isb1 isb0 gpi general purpose port indication (-) this bit indicates, that a gpp port interrupt indication is pending: gpi= ? 0 ? no general purpose port interrupt indication is pending. gpi= ? 1 ? general purpose port interrupt indication is pending. the source for this interrupt can be further determined by reading registers gpisl / gpish (refer to page 5-122). dmi dma interrupt indication (-) this bit indicates, that a dma interrupt indication is pending: dmi= ? 0 ? no dma interrupt indication is pending. dmi= ? 1 ? dma interrupt indication is pending. the source for this interrupt (channel a/b, receive/transmit) can be further determined by reading register disr (refer to page 5- 125).
peb 20525 pef 20525 register description (gstar) data sheet 5-115 2000-09-14 isa2 channel a interrupt status register 2 isa1 channel a interrupt status register 1 isa0 channel a interrupt status register 0 isb2 channel b interrupt status register 2 isb1 channel b interrupt status register 1 isb0 channel b interrupt status register 0 these bits indicate, that an interrupt indication is pending in the corresponding interrupt status register(s) isr0 / isr1 / isr2 of the serial communication controller (scc): bit= ? 0 ? no interrupt indication is pending. bit= ? 1 ? an interrupt indication is pending.
peb 20525 pef 20525 register description (gpdirl) data sheet 5-116 2000-09-14 register 4 gpdirl gpp direction register (low byte) cpu accessibility: read/write reset value: 07 h offset address: 04 h typical usage: written by cpu, evaluated by serocco-h bit76543210 gpp i/o direction control 00000 gp10dir gp9dir gp8dir register 5 gpdirh gpp direction register (high byte) cpu accessibility: read/write reset value: ff h offset address: 05 h typical usage: written by cpu evaluated by serocco-h bit76543210 gpp i/o direction control 1 gp6dir 111 gp2dir gp1dir gp0dir
peb 20525 pef 20525 register description (gpdirh) data sheet 5-117 2000-09-14 gpndir gpp pin n direction control (-) this bit selects between input and output function of the corresponding gpp pin: bit = ? 0 ? output bit = ? 1 ? input (reset value)
peb 20525 pef 20525 register description (gpdatl) data sheet 5-118 2000-09-14 register 6 gpdatl gpp data register (low byte) cpu accessibility: read/write reset value: - offset address: 06 h typical usage: written by cpu(outputs) and serocco-h(inputs), evaluated by serocco-h(outputs) and cpu(inputs) bit76543210 gpp data i/o ----- gp10dat gp9dat gp8dat register 7 gpdath gpp data register (high byte) cpu accessibility: read/write reset value: - offset address: 07 h typical usage: written by cpu(outputs) and serocco-h(inputs), evaluated by serocco-h(outputs) and cpu(inputs) bit76543210 gpp data i/o - gp6dat --- gp2dat gp1dat gp0dat
peb 20525 pef 20525 register description (gpdath) data sheet 5-119 2000-09-14 gpndat gpp pin n data i/o value (-) this bit indicates the value of the corresponding gpp pin: bit = ? 0 ? if direction is input: input level is ? low ? ; if direction is output: output level is ? low ? . bit = ? 1 ? if direction is input: input level is ? high ? ; if direction is output: output level is ? high ? .
peb 20525 pef 20525 register description (gpiml) data sheet 5-120 2000-09-14 register 8 gpiml gpp interrupt mask register (low byte) cpu accessibility: read/write reset value: 07 h offset address: 08 h typical usage: written by cpu, evaluated by serocco-h bit76543210 gpp interrupt mask bits 00000 gp10im gp9im gp8im register 9 gpimh gpp interrupt mask register (high byte) cpu accessibility: read/write reset value: ff h offset address: 09 h typical usage: written by cpu, evaluated by serocco-h bit76543210 gpp interrupt mask bits 1 gp6im 111 gp2im gp1im gp0im
peb 20525 pef 20525 register description (gpimh) data sheet 5-121 2000-09-14 gpnim gpp pin n interrupt mask (-) this bit controls the interrupt mask of the corresponding gpp pin: bit = ? 0 ? interrupt generation is enabled. an interrupt is generated on any state transition of the corresponding port pin (inputs). bit = ? 1 ? interrupt generation is disabled (reset value).
peb 20525 pef 20525 register description (gpisl) data sheet 5-122 2000-09-14 register 10 gpisl gpp interrupt status register (low byte) cpu accessibility: read only reset value: 00 h offset address: 0a h typical usage: written by serocco-h, read and evaluated by cpu bit76543210 gpp interrupt status bits 00000 gp10i gp9i gp8i register 11 gpish gpp interrupt status register (high byte) cpu accessibility: read only reset value: 00 h offset address: 0b h typical usage: written by serocco-h, read and evaluated by cpu bit76543210 gpp interrupt status bits 0 gp6i 000 gp2i gp1i gp0i
peb 20525 pef 20525 register description (gpish) data sheet 5-123 2000-09-14 gpni gpp pin n interrupt indiction (-) this bit indicates if an interrupt event occured on the corresponding gpp pin: bit = ? 0 ? no interrupt indication is pending at this pin (no state transition has occured). bit = ? 1 ? an interrupt indication is pending (a state transition occured). the interrupt indication is cleared after read access.
peb 20525 pef 20525 register description (dcmdr) data sheet 5-124 2000-09-14 register 12 dcmdr dma command register cpu accessibility: read/write reset value: 00 h offset address: 0c h typical usage: written by cpu, evaluated by serocco-h bit76543210 dma controller reset command bits rdtb 0 rdrb 0 rdta 0 rdra 0 rdtb reset dma transmit channel b rdrb reset dma receive channel b rdta reset dma transmit channel a rdra reset dma receive channel a self-clearing command bit. these bits bring the external dma support logic to the reset state: bit= ? 0 ? no reset is performed. bit= ? 1 ? reset is performed.
peb 20525 pef 20525 register description (disr) data sheet 5-125 2000-09-14 note: interrupt indications are stored even if masked in register dimr . pending interrupts get presented to the system as soon as they get unmasked. register 13 disr dma interrupt status register cpu accessibility: read only reset value: 00 h offset address: 0e h typical usage: written by serocco-h, evaluated by cpu bit76543210 dma interrupt status register 0 rbfb rdteb tdteb 0 rbfa rdtea tdtea rbfb receive buffer full channel b rbfa receive buffer full channel a if a receive buffer size is defined in registers rmbsl / rmbsh and during reception the end of the receive buffer is reached this interrupt is generated indicating that the receive buffer is full. if the external dma controller supports length protection for receive buffers itself this interrupt is obsolete. in that case, the receive buffer length check can be disabled by setting bit rmbsh :drmbs to ? 1 ? . rdteb receive dma transfer end channel b rdtea receive dma transfer end channel a this bit set to ? 1 ? indicates that a dma transfer of receive data is finished and the receive data is completely moved to the corresponding receive buffer in host memory.
peb 20525 pef 20525 register description (disr) data sheet 5-126 2000-09-14 tdteb transmit dma transfer end channel b tdtea transmit dma transfer end channel a this bit set to ? 1 ? indicates that the data is completely moved from the transmit buffer to the on-chip transmit fifo, i.e. the transmit byte count programmed in registers xbcl / xbch is reached.
peb 20525 pef 20525 register description (dimr) data sheet 5-127 2000-09-14 register 14 dimr dma interrupt mask register cpu accessibility: read/write reset value: 77 h offset address: 0f h typical usage: bit76543210 dma interrupt mask register 0 mrbfb mrdteb mtdteb 0 mrbfa mrdtea mtdtea mrbfb mask receive buffer full interrupt channel b mrbfa mask receive buffer full interrupt channel a mrdteb mask receive dma transfer end interrupt channel b mrdtea mask receive dma transfer end interrupt channel a mtdteb mask transmit dma transfer end interrupt channel b mtdtea mask transmit dma transfer end interrupt channel a if a bit in this interrupt mask register is set to ? 1 ? , the corresponding interrupt is not generated and not indicated in the corresponding bit position in the disr register. after reset all interrupts are masked.
peb 20525 pef 20525 register description (fifol) data sheet 5-128 2000-09-14 5.2.2 channel specific scc registers each register description is organized in three parts: a head with general information about reset value, access type (read/write), channel specific offset addresses and usual handling; a table containing the bit information (name of bit positions); a section containing the detailed description of each bit. register 15 fifol receive/transmit fifo (low byte) cpu accessibility: read/write reset value: - channel a channel b offset address: 10 h 60 h typical usage: xfifo: written by cpu, evaluated by serocco-h rfifo: written by serocco-h, evaluated by cpu bit76543210 rfifo/xfifo access low byte fifo(7:0) register 16 fifoh receive/transmit fifo (high byte) cpu accessibility: read/write reset value: - channel a channel b offset address: 11 h 61 h typical usage: xfifo: written by cpu, evaluated by serocco-h rfifo: written by serocco-h, evaluated by cpu bit76543210 rfifo/xfifo access high byte fifo(15:8)
peb 20525 pef 20525 register description (fifoh) data sheet 5-129 2000-09-14 receive fifo (rfifo) reading data from the rfifo can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal ? width ? . in 16-bit bus mode only 16-bit accesses to rfifo are allowed. only for a frame with odd byte count the last access can be an 8-bit access. note: the ? width ? signal is available for the p-tqfp-100-3 package only. with the p- lfbga-80-2 package only 8-bit accesses are supported. the size of the accessible part of rfifo is determined by programming the rfifo threshold level in bit field ccr3h .rfth(1:0). the threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. interrupt controlled data transfer ( gmode .edma= ? 0 ? ) up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt (see isr0 register). the address provided during an rfifo read access is not incremental; it is always 10 h for channel a or 60 h for channel b. rpf interrupt: this interrupt indicates that the adjusted receive threshold level is reached. the message is not yet complete. a fix number of bytes, dependent from the threshold level, has to be read. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl , rbch registers. the content of the rfifo is released by issuing the ? receive message complete ? command ( cmdrh .rmc). dma controlled data transfer ( gmode .edma= ? 1 ? ) if dma operation is enabled, the serocco-h autonomously requests data transfer by asserting the drr line to the external dma controller. the drr line remains active until the beginning of the last receive data byte/word transfer. for a detailed decsription of the external dma interface operation refer to ? external dma controller support ? on page 80 . transmit fifo (xfifo) writing data to the xfifo can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal ? width ? . in 16-bit bus mode only 16-bit accesses to xfifo are allowed. only for a frame with odd byte count the last access must be an 8-bit access. note: the ? width ? signal is available for the p-tqfp-100-3 package only. with the p- lfbga-80-2 package only 8-bit accesses are supported. interrupt controlled data transfer ( gmode .edma= ? 0 ? ) following an xpr (or an alls) interrupt, up to 32 bytes/16 words of new transmit data can be written into the xfifo. transmit data can be released for transmission with an
peb 20525 pef 20525 register description (fifoh) data sheet 5-130 2000-09-14 xtf command. the address provided during an xfifo write access is not incremental; it is always 10 h for channel a or 60 h for channel b. dma controlled data transfer ( gmode .edma= ? 1 ? ) if dma operation is enabled, the serocco-h autonomously requests data transfer to the xfifo by asserting the drt line to the external dma controller. the drt line remains active until the beginning of the last transmit data byte/word transfer. for a detailed description of the external dma interface operation refer to ? external dma controller support ? on page 80 .
peb 20525 pef 20525 register description (starl) data sheet 5-131 2000-09-14 register 17 starl status register (low byte) cpu accessibility: read only reset value: 00 h channel a channel b offset address: 12 h 62 h typical usage: updated by serocco-h read and evaluated by cpu bit76543210 command status transmitter status xrepe 0 0 cec 0 xdov xfw cts register 18 starh status register (high byte) cpu accessibility: read only reset value: 10 h channel a channel b offset address: 13 h 63 h typical usage: updated by serocco-h read and evaluated by cpu bit76543210 receiver status automode status 0 0 cd rli dpla wfa xrnr rrnr
peb 20525 pef 20525 register description (starh) data sheet 5-132 2000-09-14 xrepe transmit repetition executing xrepe= ? 0 ? no transmit repetition command is in execution. xrepe= ? 1 ? a xrep command (register cmdrl ) is currently in execution. cec command executing cec= ? 0 ? no command is currently in execution. the command registers cmdrl / cmdrh can be written by cpu. cec= ? 1 ? a command (written previously to registers cmdrl / cmdrh ) is currently in execution. no further command can be written to registers cmdrl / cmdrh by cpu. note: cec will stay active if the scc is in power-down mode or if no serial clock, needed for command execution, is available. xdov transmit fifo data overflow xdov= ? 0 ? less than or equal to 32 bytes have been written to the xfifo. xdov= ? 1 ? more than 32 bytes have been written to the xfifo. this bit is reset by: ? a transmitter reset command ? xres ? ? or when all bytes in the accessible half of the xfifo have been moved into the inaccessible half. xfw transmit fifo write enable xfw= ? 0 ? the xfifo is not able to accept further transmit data. xfw= ? 1 ? transmit data can be written to the xfifo. cts cts (clear to send) input signal state cts= ? 0 ? cts input signal is inactive (high level) cts= ? 1 ? cts input signal is active (low level) note: a transmit clock is necessary to detect the input level of cts . optionally this input can be programmed to generate an interrupt on signal level changes.
peb 20525 pef 20525 register description (starh) data sheet 5-133 2000-09-14 cd cd (carrier detect) input signal state cd= ? 0 ? cd input signal is low. cd= ? 1 ? cd input signal is high. note: optionally this input can be programmed to generate an interrupt on signal level changes. rli receive line inactive this bit indicates that neither flags as interframe time fill nor data are being received via the receive line. rli= ? 0 ? receive line is active, no constant high level is detected. rli= ? 1 ? receive line is inactive, i.e. more than 7 consecutive ? 1 ? are detected on the line. note: a receive clock must be provided in order to detect the receive line state. dpla dpll asynchronous this bit is only valid if the receive clock is recovered by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. in this case reception is disabled (receive abort condition) until synchronization has been regained. in addition transmission is interrupted in all cases where transmit clock is derived from the dpll (clock mode 3a, 7a). interruption of transmission is performed the same way as on deactivation of the cts signal. dpla= ? 0 ? dpll is synchronized. dpla= ? 1 ? dpll is asynchronous (re-synchronization process is started automatically). wfa wait for acknowledgement this status bit is significant in automode only. it indicates whether the automode state machine expects an acknowledging i- or s-frame for a previously sent i-frame. wfa= ? 0 ? no acknowledge i/s-frame is expected. wfa= ? 1 ? the automode state machine is waiting for an achnowledging s- or i-frame.
peb 20525 pef 20525 register description (starh) data sheet 5-134 2000-09-14 xrnr transmit rnr status this status bit is significant in automode only. it indicates the receiver status of the local station (scc). xrnr= ? 0 ? the receiver is ready and will automatically answer poll- frames with a s-frame with ?receiver-ready? indication. xrnr= ? 1 ? the receiver is not ready and will automatically answer poll-frames with a s-frame with a ?receiver-not-ready? indication. rrnr received rnr (receiver not ready) status this status bit is significant in automode only. it indicates the receiver status of the remote station. rrnr= ? 0 ? the remote station receiver is ready. rrnr= ? 1 ? the remote receiver is not ready. (a ?receiver-not-ready? indication was received from the remote station)
peb 20525 pef 20525 register description (cmdrl) data sheet 5-135 2000-09-14 the command register contains self-clearing command bits. the command bits read a ? 1 ? until the corresponding command is executed completely. for a write access to the register, the new value gets or ? ed with the current register contents. the ? cec ? bit in register starl / starh is the or-function over all command bits. register 19 cmdrl command register (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 14 h 64 h typical usage: written by cpu, evaluated by serocco-h bit76543210 timer transmitter commands sti tres xif xres xf xme xrep 0 register 20 cmdrh command register (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 15 h 65 h typical usage: written by cpu, evaluated by serocco-h bit76543210 receiver commands rmc rnr 0 0 rsuc 0 0 rres
peb 20525 pef 20525 register description (cmdrh) data sheet 5-136 2000-09-14 sti start timer command self-clearing command bit: hdlc automode: in hdlc automode the timer is used internally for the autonomous protocol support functions. the timer is started automatically by the scc when an i-frame is sent out and needs to be acknowledged. if the ? sti ? command is issued by software: sti= ? 1 ? an s-frame with poll bit set is sent out and the internal timer is started expecting an acknowledge from the remote station via an i- or s-frame. the timer is stopped after receiving an acknowledge otherwise the timer expires generating a timer interrupt. note: in hdlc automode, bit ? tmd ? in register timr3 must be set to ? 1 ? all protocol modes except hdlc automode: in these modes the timer is operating as a general purpose timer. sti= ? 1 ? this commands starts timer operation. the timer can be stopped by setting bit ? tres ? . note: bit ? tmd ? in register timr3 must be cleared for proper operation tres timer reset self-clearing command bit. this bit deactivates timer operation: tres= ? 0 ? timer operation enabled. tres= ? 1 ? timer operation stopped. xif transmit i-frame self-clearing command bit. this command bit is significant in hdlc automode only. xif= ? 1 ? initiates the transmission of an i-frame in auto-mode. additional to the opening flag, the address and control fields of the frame are added by serocco-h.
peb 20525 pef 20525 register description (cmdrh) data sheet 5-137 2000-09-14 xres transmitter reset command self-clearing command bit: xres= ? 1 ? the scc transmit fifo is cleared and the transmitter protocol engines are reset to their initial state. a transmitter reset command is recommended after all changes in protocol mode configurations (e.g. switching between sub-modes of hdlc). xf transmit frame this self-clearing command bit is significant in interrupt driven operation only ( gmode .edma= ? 0 ? ). xf= ? 1 ? after having written up to 32 bytes to the xfifo, this command initiates transmission. in packet oriented protocols like hdlc/ppp the opening flag is automatically added by serocco-h. if the end of the packet is part of the transmit data, bit ? xme ? should be set in addition. dma mode after having written the length of the data block to be transmitted to registers xbcl and xbch , this command initiates the data transfer from host memory to serocco-h by dma. transmission on the serial side starts as soon as 32 bytes are transferred to the xfifo or the transmit byte counter value is reached. xme transmit message end self-clearing command bit: xme= ? 1 ? indicates that the data block written last to the xfifo contains the end of the packet. this bit should always be set in conjunction with a transmit command ( ? xf ? or ? xif ? ). xrep transmission repeat command self-clearing command bit: xrep= ? 1 ? if bit ? xrep ? is set together with bit ? xme ? and ? xf ? , serocco-h repeatedly transmits the contents of the xfifo (1..32 bytes). the cyclic transmission can be stopped with the ? xres ? command.
peb 20525 pef 20525 register description (cmdrh) data sheet 5-138 2000-09-14 rmc receive message complete self-clearing command bit: rmc= ? 1 ? with this bit the cpu indicates to serocco-h that the current receive data has been fetched out of the rfifo. thus the corresponding space in the rfifo can be released and re-used by serocco-h for further incoming data. rnr receiver not ready command non self-clearing command bit: this command bit is significant in hdlc automode only. rnr= ? 0 ? forces the receiver to enter its ? receiver-ready ? state. the receiver acknowledges received poll or i-frames with a ? receiver-ready ? indication. rnr= ? 1 ? forces the receiver to enter its ? receiver-not-ready ? state. the receiver acknowledges received poll or i-frames with a ? receiver-not-ready ? indication. rsuc reset signaling unit counter self-clearing command bit: this command bit is significant if hdlc ss7 mode is selected. rsuc= ? 1 ? the signaling system #7 (ss7) unit counter is reset. rres receiver reset command self-clearing command bit: rres= ? 1 ? the scc receive fifo is cleared and the receiver protocol engines are reset to their initial state. the scc receive fifo accepts new receive data from the protocol engine immediately after receiver reset procedure. it is recommended to disable data reception before issuing a receiver reset command by setting bit ccr3l .rac = ? 0 ? and enabling data reception afterwards. a ? receiver reset ? command is recommended after all changes in protocol mode configurations.
peb 20525 pef 20525 register description (ccr0l) data sheet 5-139 2000-09-14 register 21 ccr0l channel configuration register 0 (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 16 h 66 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. clock mode selection vis psd 0 toe ssel cm(2:0) register 22 ccr0h channel configuration register 0 (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 17 h 67 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 power line coding pu sc(2:0) 0 0 0 0
peb 20525 pef 20525 register description (ccr0h) data sheet 5-140 2000-09-14 vis masked interrupts visible vis= ? 0 ? masked interrupt status bits are not displayed in the interrupt status registers ( isr0 .. isr2 ). vis= ? 1 ? masked interrupt status bits are visible and automatically cleared after interrupt status register ( isr0 .. isr2 ) read access. note: interrupts masked in registers imr0 .. imr2 will not generate an interrupt. psd dpll phase shift disable this option is only applicable in the case of nrz or nrzi line encoding is selected. psd= ? 0 ? normal dpll operation. psd= ? 1 ? the phase shift function of the dpll is disabled. the windows for phase adjustment are extended. toe transmit clock out enable for clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock can be monitored on pin txclk as an output signal. in clock mode 5, a time slot control signal marking the active transmit time slot is output on pin txclk. bit ? toe ? is invalid for all other clock modes. toe= ? 0 ? txclk pin is input. toe= ? 1 ? txclk pin is switched to output function if applicable for the selected clock mode. ssel clock source select distinguishes between the ? a ? and ? b ? option of clock modes 0, 2, 3, 5, 6 and 7. ssel= ? 0 ? option ? a ? is selected. ssel= ? 1 ? option ? b ? is selected.
peb 20525 pef 20525 register description (ccr0h) data sheet 5-141 2000-09-14 cm(2:0) clock mode this bit field selects one of main clock modes 0..7. for a detailed description of the clock modes refer to chapter 3.2.3 cm = ? 000 ? clock mode 0 cm = ? 001 ? clock mode 1 cm = ? 010 ? clock mode 2 cm = ? 011 ? clock mode 3 cm = ? 100 ? clock mode 4 cm = ? 101 ? clock mode 5 (time-slot oriented clocking modes) cm = ? 110 ? clock mode 6 cm = ? 111 ? clock mode 7 pu power up pu= ? 0 ? the scc is in ? power-down ? mode. the protocol engines are switched off (standby) and no operation is performed. this may be used to save power when scc is not in use. note: the scc transmit fifo accepts transmit data even in ? power-down ? mode. pu= ? 1 ? the scc is in ? power-up ? mode. sc(2:0) serial port configuration
peb 20525 pef 20525 register description (ccr0h) data sheet 5-142 2000-09-14 this bit field selects the line coding of the serial port. note, that special operation modes and settings may require or exclude operation in special line coding modes. refer to the ? prerequisites ? in the dedicated mode descriptions. sc = ? 000 ? nrz data encoding sc = ? 001 ? bus configuration, timing mode 1 (nrz data encoding) sc = ? 010 ? nrzi data encoding sc = ? 011 ? bus configuration, timing mode 2 (nrz data encoding) sc = ? 100 ? fm0 data encoding sc = ? 101 ? fm1 data encoding sc = ? 110 ? manchester data encoding sc = ? 111 ? reserved note: if bus configuration mode is selected, only nrz data encoding is supported.
peb 20525 pef 20525 register description (ccr1l) data sheet 5-143 2000-09-14 register 23 ccr1l channel configuration register 1 (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 18 h 68 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. crl c32 soc(1:0) sflg div ods 0 register 24 ccr1h channel configuration register 1 (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 19 h 69 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. 0 icd 0 rts frts fcts cas tscm
peb 20525 pef 20525 register description (ccr1h) data sheet 5-144 2000-09-14 crl crc reset value this bit defines the initial value of the internal transmit/receive crc generators: crl= ? 0 ? initial value is 0xffff h (16 bit crc), 0xffffffff h (32 bit crc). this is the default value for most hdlc/ppp applications. crl= ? 1 ? initial value is 0x0000 h (16 bit crc), 0x00000000 h (32 bit crc). c32 crc 32 select this bit enables 32-bit crc operation for transmit and receive. c32= ? 0 ? 16-bit crc-ccitt generation/checking. c32= ? 1 ? 32-bit crc generation/checking. note: the internal ? valid frame ? criteria is updated depending on the selected number of crc-bytes. soc(1:0) serial output control this bit field selects the rts signal output function. (this bit field is only valid in bus configuration modes selected via bit field sc(2:0) in register ccr0h ). soc = ? 0x ? rts ouput signal is active during transmission of a frame (active low). soc = ? 10 ? rts ouput signal is always inactive (high). soc = ? 11 ? rts ouput signal is active during reception of a frame (active low). sflg shared flags transmission this bit enables ? shared flag transmission ? in hdlc protocol mode. if another transmit frame begin is stored in the scc transmit fifo, the closing flag of the preceding frame becomes the opening flag of the next frame (shared flags): sflg = ? 0 ? shared flag transmission disabled. sflg = ? 1 ? shared flag transmission enabled. note: the receiver always supports shared flags and shared zeros of consecutive flags.
peb 20525 pef 20525 register description (ccr1h) data sheet 5-145 2000-09-14 div data inversion this bit is only valid if nrz data encoding is selected via bit field sc(2:0) in register ccr0h . div= ? 0 ? no data inversion. div= ? 1 ? data is transmitted/received inverted (on a per bit basis). in hdlc and hdlc synchronous ppp modes the continuous ? 1 ? idle sequence is not inverted. thus it is recommended to select the flag sequence for interframe time fill transmission ( ccr2h :itf = ? 1 ? ), which is inverted. ods output driver select the transmit data output pin txd can be configured as push/pull or open drain output chracteristic. ods= ? 0 ? txd pin is open drain output. ods= ? 1 ? txd pin is push/pull output. icd invert carrier detect pin polarity icd= ? 0 ? carrier detect (cd) input pin is active high. icd= ? 1 ? carrier detect (cd) input pin is active low. rts request to send pin control the request to send pin rts can be controlled by serocco-h as an output autonomously or via setting/clearing bit ? rts ? . this bit is not valid in clock mode 4. rts= ? 0 ? pin rts (output) pin is controlled by serocco-h autonomously. rts is activated during transmission. in bus configuration mode the functionality depends on bit field ? soc ? setting. note: for autonomous rts pin control a transmit clock is necessary. rts= ? 1 ? pin rts can be controlled by software. the output level of this pin depends on bit ? frts ? .
peb 20525 pef 20525 register description (ccr1h) data sheet 5-146 2000-09-14 frts flow control (using signal rts ) bit ? frts ? together with bit ? rts ? determine the function of signal rts : rts, frts 0, 0 pin rts is controlled by serocco-h autonomously. rts is activated (low) as soon as transmit data is available within the scc transmit fifo. 0, 1 pin rts is controlled by serocco-h autonomously supporting bi-directional data flow control. rts is activated (low) if the shadow part of the scc receive fifo is empty and de-activated (high) when the scc receive fifo fill level reaches its receive fifo threshold. 1, 0 forces pin rts to active state (low). 1, 1 forces pin rts to inactive state (high). fcts flow control (using signal cts ) this bit controls the function of pin cts . fcts = ? 0 ? the transmitter is stopped if cts input signal is inactive (high) and enabled if active (low). fcts = ? 1 ? the transmitter is enabled, disregarding cts input signal. cas carrier detect auto start cas = ? 0 ? the cd pin is used as general input. in clock mode 1, 4 and 5, clock mode specific control signals must be provided at this pin (receive strobe, receive gating rcg , frame sync clock fsc ). a pull-up/down resistor is recommended if unused. cas = ? 1 ? the cd pin enables/disables the receiver for data reception. (polarity of cd pin can be configured via bit ? icd ? .) note: (1) in clock mode 1, 4 and 5 this bit must be set to ? 0 ? . (2) a receive clock must be provided for the autonomous receiver control function of the cd input pin.
peb 20525 pef 20525 register description (ccr1h) data sheet 5-147 2000-09-14 tscm time slot control mode this bit controls internal counter operation in time slot oriented clock mode 5: tscm= ? 0 ? the internal counter keeps running, restarting with zero after being expired. tscm= ? 1 ? the internal counter stops at its maximum value and restarts with the next frame sync pulse again.
peb 20525 pef 20525 register description (ccr2l) data sheet 5-148 2000-09-14 register 25 ccr2l channel configuration register 2 (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 1a h 6a h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. mds(1:0) adm nrm pppm(1:0) tlpo tlp register 26 ccr2h channel configuration register 2 (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 1b h 6b h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. mcs ept npre(1:0) itf 0 oin xcrc
peb 20525 pef 20525 register description (ccr2h) data sheet 5-149 2000-09-14 mds(1:0) mode select this bit field selects the hdlc protocol sub-mode including the ? extended transparent mode ? . mds = ? 00 ? automode. mds = ? 01 ? address mode 2. mds = ? 10 ? address mode 0/1. (option ? 0 ? or ? 1 ? is selected via bit ? adm ? .) mds = ? 11 ? extended transparent mode (bit transparent transmission/ reception). note: ? mds(1:0) ? must be set to ? 10 ? if any ppp mode is enabled via bit field ? pppm ? or if ss7 is enabled via bit ? ess7 ? in register ccr3l . adm address mode select the meaning of this bit depends on the selected protocol sub-mode: automode, address mode 2: determines the address field length of an hdlc frame. adm = ? 0 ? 8-bit address field. adm = ? 1 ? 16-bit address field. address mode 0/1: determines whether address mode 0 or 1 is selected. adm = ? 0 ? address mode 0 (no address recognition). adm = ? 1 ? address mode 1 (high byte address recognition). extended transparent mode: adm = ? 1 ? recommended setting nrm normal response mode this bit is valid in hdlc automode operation only and determines the function of the automode lap-controller: nrm = ? 0 ? full-duplex lap-b / lap-d operation. nrm = ? 1 ? half-duplex normal response mode (nrm) operation.
peb 20525 pef 20525 register description (ccr2h) data sheet 5-150 2000-09-14 pppm(1:0) ppp mode select this bit field enables and selects the hdlc ppp protocol modes: pppm = ? 00 ? no ppp protocol operation. the hdlc sub-mode is determined by bit field ?mds?. pppm = ? 01 ? octet synchronous ppp protocol operation. pppm = ? 10 ? reserved pppm = ? 11 ? bit synchronous ppp protocol operation. note: ? address mode 0 ? must be selected by setting bit field ? mds(1:0) ? to ? 10 ? and bit ? adm ? to ? 0 ? if any ppp mode is enabled. tlpo test loop out function this bit is only valid if test loop is enabled and controls whether test loop transmit data is driven on pin txd: tlpo = ? 0 ? test loop transmit data is driven to txd pin. tlpo = ? 1 ? test loop transmit data is not driven to txd pin. txd pin is idle ? 1 ? . depending on the selected output characteristic the pin is high impedance (bit ccr1l .ods = ? 0 ? ) or driving high ( ccr1l .ods = ? 1 ? ). tlp test loop this bit controls the internal test loop between transmit and receive data signals. the test loop is closed at the far end of serial transmit and receive line just before the respective txd and rxd pins: tlp = ? 0 ? test loop disabled. tlp = ? 1 ? test loop enabled. the software is responsible to select a clock mode which allows correct reception of transmit data depending on the external clock supply. transmit data is sent out via pin txd if not disabled with bit ? tlpo ? . the receive input pin rxd is internally disconnected during test loop operation.
peb 20525 pef 20525 register description (ccr2h) data sheet 5-151 2000-09-14 mcs modulo count select this bit is valid in hdlc automode operation only and determines the control field format: mcs = ? 0 ? basic operation, one byte control field (modulo 8 counter operation). mcs = ? 1 ? extended operation, two bytes control field (modulo 128 counter operation). ept enable preamble transmission this bit enables preamble transmission. the preamble is started after interframe time fill (itf) transmission is stopped because a new frame is ready to be transmitted. the preamble pattern consists of 8 bits defined in register preamb , which is sent repetitively. the number of repetitions is determined by bit field ? pre(1:0) ? : ept= ? 0 ? preamble transmission is disabled. ept= ? 1 ? preamble transmission is enabled. note: preamble operation does not influence hdlc shared flag transmission if enabled. npre(1:0) number of preamble repetitions this bit field determines the number of preambles transmitted: npre = ? 00 ? 1 preamble. npre = ? 01 ? 2 preambles. npre = ? 10 ? 4 preambles. npre = ? 11 ? 8 preambles. itf interframe time fill this bit selects the idle state of the transmit pin txd: itf= ? 0 ? continuous logical ? 1 ? is sent during idle phase. itf= ? 1 ? continuous flag sequences are sent ( ? 01111110 ? flag pattern). note: it is recommended to clear bit ? itf ? in bus configuration modes, i.e. continuous ? 1 ? s are sent as idle sequence and data encoding is nrz.
peb 20525 pef 20525 register description (ccr2h) data sheet 5-152 2000-09-14 oin one insertion in hdlc mode a one-insertion mechanism similar to the zero-insertion can be activated: oin= ? 0 ? the ?1? insertion mechanism is disabled. oin= ? 1 ? in transmit direction a logical ?1? is inserted to the serial data stream after 7 consecutive zeros. in receive direction a ?1? is deleted from the receive data stream after receiving 7 consecutive zeros. this enables clock information to be recovered from the receive data stream by means of a dpll, even in the case of nrz data encoding, because a transition at bit cell boundary occurs at least every 7 bits. xcrc transmit crc checking mode xcrc= ? 0 ? the transmit checksum (2 or 4 bytes) is generated and appended to the transmit data automatically. xcrc= ? 1 ? the transmit checksum is not generated automatically. the checksum is expected to be provided by software as the last 2 or 4 bytes in the transmit data buffer.
peb 20525 pef 20525 register description (ccr3l) data sheet 5-153 2000-09-14 register 27 ccr3l channel configuration register 3 (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 1c h 6c h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. elc afx csf suet rac 0 0 ess7 register 28 ccr3h channel configuration register 3 (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 1d h 6d h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 misc. 0 drcrc rcrc radd 0 0 rfth(1:0)
peb 20525 pef 20525 register description (ccr3h) data sheet 5-154 2000-09-14 elc enable length check this bit is only valid in hdlc ss7 mode: if the number of received octets exceeds 272 + 7 within one signaling unit, reception is aborted and bit rsta .rab is set. elc= ? 0 ? length check disabled. elc= ? 1 ? length check enabled. afx automatic fisu transmission this bit is only valid in hdlc ss7 mode: after the contents of the transmit fifo (xfifo) has been transmitted completely, fisus are transmited automatically. these fisus contain the fsn and bsn of the last transmitted signaling unit (provided in xfifo). afx= ? 0 ? automatic fisu transmission disabled. afx= ? 1 ? automatic fisu transmission enabled. csf compare status field this bit is only valid in hdlc ss7 mode: if the status fields of consecutive lssus are equal, only the first will be stored and every following is ignored csf= ? 0 ? compare is disabled, all received lssus are stored in the receive fifo. csf= ? 1 ? compare is enabled, only the first one of consecutive equal lssus is stored in the receive fifo. suet signalling unit counter threshold this bit is only valid in hdlc ss7 mode: defines the number of signaling units received in error that will cause an error rate high indication ( isr1 .suex). suet= ? 0 ? threshold is 64 errored signaling units. suet= ? 1 ? threshold is 32 errored signaling units.
peb 20525 pef 20525 register description (ccr3h) data sheet 5-155 2000-09-14 rac receiver active switches the receiver between operational/inoperational states: rac= ? 0 ? receiver inactive, receive line is ignored. rac= ? 1 ? receiver active. ess7 enable ss7 mode this bit is only valid in hdlc mode only. ess7= ? 0 ? disable signaling system #7 (ss7) support. ess7= ? 1 ? enable signaling system #7 (ss7) support. note: if ss7 mode is enabled, ? address mode 0 ? must be selected by setting bit field ccr2l :mds(1:0) to ? 10 ? and bit ccr2l :adm to ? 0 ? . drcrc disable receive crc checking drcrc= ? 0 ? the receiver expects a 16 or 32 bit crc within a hdlc frame. crc processing depends on the setting of bit ? rcrc ? . frames shorter than expected are marked ? invalid ? or are discarded (refer to rsta description). drcrc= ? 1 ? the receiver does not expect any crc within a hdlc frame. the criteria for ? valid frame ? indication is updated accordingly (refer to rsta description). bit ? rcrc ? is ignored. rcrc receive crc checking mode rcrc= ? 0 ? the received checksum is evaluated, but not forwarded to the receive fifo. rcrc= ? 1 ? the received checksum (2 or 4 bytes) is evaluated and forwarded to the receive fifo as data.
peb 20525 pef 20525 register description (ccr3h) data sheet 5-156 2000-09-14 radd receive address forward to rfifo this bit is only valid ? if an hdlc sub-mode with address field support is selected (automode, address mode 2, address mode 1) ? in ss7 mode radd= ? 0 ? the received hdlc address field (either 8 or 16 bit, depending on bit ? adm ? ) is evaluated, but not forwarded to the receive fifo. in ss7 mode, the signaling unit fields ? fsn ? and ? bsn ? are not forwarded to the receive fifo. radd= ? 1 ? the received hdlc address field (either 8 or 16 bit, depending on bit ? adm ? ) is evaluated and forwarded to the receive fifo. in ss7 mode, the signaling unit fields ? fsn ? and ? bsn ? are forwarded to the receive fifo. rfth(1:0) receive fifo threshold this bit field defines the level up to which the scc receive fifo is filled with valid data before an ? rpf ? interrupt is generated. (in case of a ? frame end ? condition the serocco-h notifies the cpu immediately, disregarding this threshold.) rfth(1:0) threshold level in number of data bytes. ? 00 ? 32 byte ? 01 ? 16 byte ? 10 ? 4 byte ? 11 ? 2 byte
peb 20525 pef 20525 register description (preamb) data sheet 5-157 2000-09-14 register 29 preamb preamble register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 1e h 6e h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 preamble pattern pre(7:0) pre(7:0) preamble this bit field determines the preamble pattern which is send out during preamble transmission. note: in hdlc-mode, zero-bit insertion is disabled during preamble transmission.
peb 20525 pef 20525 register description (accm0) data sheet 5-158 2000-09-14 register 30 accm0 ppp async control character map 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 20 h 70 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character control map 07..00 07 06 05 04 03 02 01 00 register 31 accm1 ppp async control character map 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 21 h 71 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character control map 0f..08 0f 0e 0d 0c 0b 0a 09 08
peb 20525 pef 20525 register description (accm2) data sheet 5-159 2000-09-14 register 32 accm2 ppp async control character map2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 22 h 72 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character control map 17..10 17 16 15 14 13 12 11 10 register 33 accm3 ppp async control character map 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 23 h 73 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character control map 1f..18 1f 1e 1d 1c 1b 1a 19 18
peb 20525 pef 20525 register description (accm3) data sheet 5-160 2000-09-14 accm async character control map this bit field is valid in hdlc octet-synchronous ppp mode only: each bit selects the corresponding character (indicated as hex value 1f h ..00 h in the register description table) as control character which has to be mapped into the transmit data stream.
peb 20525 pef 20525 register description (udac0) data sheet 5-161 2000-09-14 register 34 udac0 user defined ppp async control character map 0 cpu accessibility: read/write reset value: 7e h channel a channel b offset address: 24 h 74 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character 0 ac0 register 35 udac1 user defined ppp async control character map 1 cpu accessibility: read/write reset value: 7e h channel a channel b offset address: 25 h 75 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character 1 ac1
peb 20525 pef 20525 register description (udac2) data sheet 5-162 2000-09-14 register 36 udac2 user defined ppp async control character map 2 cpu accessibility: read/write reset value: 7e h channel a channel b offset address: 26 h 76 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character 2 ac2 register 37 udac3 user defined ppp async control character map 3 cpu accessibility: read/write reset value: 7e h channel a channel b offset address: 27 h 77 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 async character 3 ac3
peb 20525 pef 20525 register description (udac3) data sheet 5-163 2000-09-14 ac3..0 user defined async character control map this bit field is valid in hdlc octet-synchronous ppp mode only: these bit fields define user determined characters as control characters which have to be mapped into the transmit data stream. in register accm only characters 00 h ..1f h can be selected as control characters. register udac allows to specify any four characters in the range 00 h ..ff h . the default value is a 7e h flag which must be always mapped. thus no additional character is mapped if 7e h ? s are programed to bit fields ac3...0 (reset value). (7e h is mapped automatically, even if not defined via a ac bit field.)
peb 20525 pef 20525 register description (ttsa0) data sheet 5-164 2000-09-14 register 38 ttsa0 transmit time slot assignment register 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 28 h 78 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 tx clock shift 000 00 tcs(2:0) register 39 ttsa1 transmit time slot assignment register 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 29 h 79 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 tx time slot number tepcm ttsn(6:0)
peb 20525 pef 20525 register description (ttsa2) data sheet 5-165 2000-09-14 register 40 ttsa2 transmit time slot assignment register 2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2a h 7a h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 transmit channel capacity tcc(7:0) register 41 ttsa3 transmit time slot assignment register 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2b h 7b h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 transmit channel capacity 0000000tcc8
peb 20525 pef 20525 register description (ttsa3) data sheet 5-166 2000-09-14 the following register bit fields allow flexible assignment of bit- or octet-aligned transmit time-slots to the serial channel. for more detailed information refer to chapters ? clock mode 5a (time slot mode) ? on page 56 and ? clock mode 5b (octet sync mode) ? on page 63 . tcs(2:0) transmit clock shift this bit field determines the transmit clock shift. tepcm enable pcm mask transmit this bit selects the additional transmit pcm mask (refer to register pcmtx0 .. pcmtx3 ): tepcm= ? 0 ? standard time-slot configuration. tepcm= ? 1 ? the time-slot width is constant 8 bit, bit fields ? ttsn ? and ? tcs ? determine the offset of the pcm mask and ? tcc ? is ignored. each time-slot selected via register pcmtx0 .. pcmtx3 is an active transmit timeslot. ttsn(6:0) transmit time slot number this bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): offset = 1+ttsn*8 + tcs (1..1024 clocks) tcc(8:0) transmit channel capacity this bit field determines the transmit time-slot width in standard time-slot configuration (bit tepcm= ? 0 ? ): number of bits = tcc + 1, (1..512 bits/time-slot)
peb 20525 pef 20525 register description (rtsa0) data sheet 5-167 2000-09-14 register 42 rtsa0 receive time slot assignment register 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2c h 7c h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 rx clock shift 000 00 rcs(2:0) register 43 rtsa1 receive time slot assignment register 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2d h 7d h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 rx time slot number repcm rtsn(6:0)
peb 20525 pef 20525 register description (rtsa2) data sheet 5-168 2000-09-14 register 44 rtsa2 receive time slot assignment register 2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2e h 7e h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive channel capacity rcc(7:0) register 45 rtsa3 receive time slot assignment register 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 2f h 7f h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive channel capacity 0 0 0 0 0 0 0 rcc8
peb 20525 pef 20525 register description (rtsa3) data sheet 5-169 2000-09-14 the following register bit fields allow flexible assignment of bit- or octet-aligned receive time-slots to the serial channel. for more detailed information refer to chapters ? clock mode 5a (time slot mode) ? on page 56 and ? clock mode 5b (octet sync mode) ? on page 63 . rcs(2:0) receive clock shift this bit field determines the receive clock shift. repcm enable pcm mask receive this bit selects the additional receive pcm mask (refer to register pcmrx0 .. pcmrx3 ): repcm= ? 0 ? standard time-slot configuration. repcm= ? 1 ? the time-slot width is constant 8 bit, bit fields ?rtsn? and ?rcs? determine the offset of the pcm mask and ?rcc? is ignored. each time-slot selected via register pcmrx0 .. pcmrx3 is an active receive timeslot. rtsn(6:0) receive time slot number this bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): offset = 1+rtsn*8 + rcs (1..1024 clocks) rcc(8:0) receive channel capacity this bit field determines the receive time-slot width in standard time-slot configuration (bit repcm= ? 0 ? ): number of bits = rcc + 1, (1..512 bits/time-slot)
peb 20525 pef 20525 register description (pcmtx0) data sheet 5-170 2000-09-14 register 46 pcmtx0 pcm mask transmit direction register 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 30 h 80 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 pcm mask for transmit direction t07 t06 t05 t04 t03 t02 t01 t00 register 47 pcmtx1 pcm mask transmit direction register 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 31 h 81 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 pcm mask for transmit direction t15 t14 t13 t12 t11 t10 t09 t08
peb 20525 pef 20525 register description (pcmtx2) data sheet 5-171 2000-09-14 register 48 pcmtx2 pcm mask transmit direction register 2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 32 h 82 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 pcm mask for transmit direction t23 t22 t21 t20 t19 t18 t17 t16 register 49 pcmtx3 pcm mask transmit direction register 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 33 h 83 h typical usage: written by cpu; read and evaluated by serocco-h bit151413121110 9 8 pcm mask for transmit direction t31 t30 t29 t28 t27 t26 t25 t24
peb 20525 pef 20525 register description (pcmtx3) data sheet 5-172 2000-09-14 pcmtx pcm mask for transmit direction this bit field is valid in clock mode 5 only and the pcm mask must be enabled via bit ? tepcm ? in register ttsa1 . each bit selects one of 32 (8-bit) transmit time-slots. the offset of time- slot zero to the frame sync pulse can be programmed via register ttsa1 bit field ? ttsn ? .
peb 20525 pef 20525 register description (pcmrx0) data sheet 5-173 2000-09-14 register 50 pcmrx0 pcm mask receive direction register 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 34 h 84 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 pcm mask for receive direction r07 r06 r05 r04 r03 r02 r01 r00 register 51 pcmrx1 pcm mask receive direction register 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 35 h 85 h typical usage: written by cpu; read and evaluated by serocco-h bit151413121110 9 8 pcm mask for receive direction r15 r14 r13 r12 r11 r10 r09 r08
peb 20525 pef 20525 register description (pcmrx2) data sheet 5-174 2000-09-14 register 52 pcmrx2 pcm mask receive direction register 2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 36 h 86 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 pcm mask for receive direction r23 r22 r21 r20 r19 r18 r17 r16 register 53 pcmrx3 pcm mask receive direction register 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 37 h 87 h typical usage: written by cpu; read and evaluated by serocco-h bit151413121110 9 8 pcm mask for receive direction r31 r30 r29 r28 r27 r26 r25 r24
peb 20525 pef 20525 register description (pcmrx3) data sheet 5-175 2000-09-14 pcmrx pcm mask for receive direction this bit field is valid in clock mode 5 only and the pcm mask must be enabled via bit ? repcm ? in register rtsa1 . each bit selects one of 32 (8-bit) receive time-slots. the offset of time- slot zero to the frame sync pulse can be programmed via register rtsa1 bit field ? rtsn ? .
peb 20525 pef 20525 register description (brrl) data sheet 5-176 2000-09-14 register 54 brrl baud rate register (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 38 h 88 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 baud rate generator factor n 0 0 brn(5:0) register 55 brrh baud rate register (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 39 h 89 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 baud rate generator factor m 0000 brm(3:0)
peb 20525 pef 20525 register description (brrh) data sheet 5-177 2000-09-14 brm(3:0) baud rate factor ? m ? brn(5:0) baud rate factor ? n ? these bit fields determine the division factor of the internal baud rate generator. the baud rate generator input clock and the usage of baud rate generator output depends on the selected clock mode. the division factor k is calculated by: with m=0..15 and n=0..63. kn1 + 2 m = f brg f in k =
peb 20525 pef 20525 register description (timr0) data sheet 5-178 2000-09-14 register 56 timr0 timer register 0 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3a h 8a h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 timer value tvalue(7:0) register 57 timr1 timer register 1 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3b h 8b h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 timer value tvalue(15:0)
peb 20525 pef 20525 register description (timr2) data sheet 5-179 2000-09-14 register 58 timr2 timer register 2 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3c h 8c h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 timer value tvalue(23:16) register 59 timr3 timer register 3 cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3d h 8d h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 timer configuration src 0 0 tmd 0 cnt(2:0)
peb 20525 pef 20525 register description (timr3) data sheet 5-180 2000-09-14 src clock source (valid in clock mode 5 only) this bit selects the clock source of the internal timer: src = ? 0 ? the timer is clocked by the effective transmit clock. src = ? 1 ? the timer is clocked by the frame-sync synchronization signal supplied via the fsc pin in clock mode 5. tmd timer mode this bit must be set to ? 1 ? if hdlc automode operation is selected. in all other protocol modes it must remain ? 0 ? : tmd= ? 0 ? the timer is controlled by the cpu via access to registers cmdrl and timr0 .. timr3 . the timer can be started any time by setting bit ? sti ? in register cmdrl . after the timer has expired it generates a timer interrupt. the timer can be stopped any time by setting bit ? tres ? in register cmdrl to ? 1 ? . tmd= ? 1 ? the timer is used by the serocco-h for protocol specific time-out and retry transactions in hdlc automode. cnt(2:0) counter the meaning of this bit field depends on the selected protocol mode. in hdlc automode, with bit tmd= ? 1 ? : retry counter (in hdlc protocol known as ? n2 ? ): bit field ? cnt ? indicates the number of s-command frames (with poll bit set) which are transmitted autonomously by serocco-h after every expiration of the time out period ? t ? (determined by ? tvalue ? ), in case an i-frame gets not acknowledged by the opposite station. the maximum value is 6 s-command frames. if ? cnt ? is set to ? 7 ? , the number of s-commands is unlimited in case of no acknowledgement. in all other modes, with bit tmd= ? 0 ? : restart counter : bit field ? cnt ? indicates the number of automatic restarts which are performed by serocco-h after every expiration of the time-out period ? t ? , in case the timer is not stopped by setting bit ? tres ? in register cmdrl to ? 1 ? . the maximum value is 6 restarts. if ? cnt ? is set to ? 7 ? , a timer interrupt is generated periodically with time period ? t ? determined by bit field ? tvalue ? .
peb 20525 pef 20525 register description (timr3) data sheet 5-181 2000-09-14 tvalue (23:0) timer expiration value this bit field determines the timer expiration period ? t ? : ( ? cp ? is the clock period, depending on bit ? src ? .) ttvalue1 + cp =
peb 20525 pef 20525 register description (xad1) data sheet 5-182 2000-09-14 register 60 xad1 transmit address 1 register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3e h 8e h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 transmit address (high) xad1 (high byte) 0 xad1_0 or xad1 (command) register 61 xad2 transmit address 2 register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 3f h 8f h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 transmit address (low) xad2 (low byte) or xad2 (response)
peb 20525 pef 20525 register description (xad2) data sheet 5-183 2000-09-14 xad1 and xad2 bit fields are valid in hdlc modes with automatic address field handling only (automode, address mode 1, address mode 2). they can be programmed with one individual address byte which is inserted automatically into the address field (8 or 16 bit) of a hdlc transmit frame. the function depends on the selected protocol mode and address field size (bit ? adm ? in register ccr2l ). xad1 transmit address 1 ? 2-byte address field: bit field xad1 constitutes the high byte of the 2-byte address field. bit 1 must be set to ? 0 ? . according to the isdn lap-d protocol, bit 1 is interpreted as the c/r (command/response) bit. this bit is manipulated automatically by serocco-h according to the setting of bit ? cri ? in register rah1 . the following is the c/r value (on bit 1), when: - transmitting commands: ? 1 ? (if ? cri ? = ? 1 ? ) ; ? 0 ? (if ? cri ? = ? 0 ? ) - transmitting responses: ? 0 ? (if ? cri ? = ? 1 ? ) ; ? 1 ? (if ? cri ? = ? 0 ? ) (in isdn lap-d, the high byte is known as ? sapi ? .) in accordance with the hdlc protocol, bit ? xad1_0 ? should be set to ? 0 ? , to indicate that the address field contains (at least) one more byte. ? 1-byte address field: according to the x.25 lap-b protocol, xad1 is the address of a ? command ? frame. xad2 transmit address 2 ? 2-byte address field: bit field xad2 constitutes the low byte of the 2-byte address field. (in isdn lap-d, the low byte is known as ? tei ? .) ? 1-byte address field: according to the x.25 lap-b protocol, xad2 is the address of a ? response ? frame.
peb 20525 pef 20525 register description (ral1) data sheet 5-184 2000-09-14 register 62 ral1 receive address 1 low register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 40 h 90 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive address 1 (low) ral1 ral1 register 63 rah1 receive address 1 high register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 41 h 91 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive address 1 (high) rah1 cri rah1_0 or rah1
peb 20525 pef 20525 register description (ral2) data sheet 5-185 2000-09-14 register 64 ral2 receive address 2 low register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 42 h 92 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive address 2 (low) ral2 register 65 rah2 receive address 2 high register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 43 h 93 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive address 2 (high) rah2
peb 20525 pef 20525 register description (rah2) data sheet 5-186 2000-09-14 in operating modes that provide address recognition, the high/low byte of the received address is compared with the individually programmable values in register rah2 / ral2 / rah1 / ral1 . this addresses can be masked on a per bit basis by setting the corresponding bits in registers amral1 / amrah1 / amral2 / amrah2 to allow extended broadcast address recognition. this feature is applicable to all hdlc sub-modes with address recognition. rah1 receive address 1 byte high in hdlc automode bit ? 1 ? is reserved for ? cri ? (command response interpretation). in all other modes rah1 is an 8 bit address. cri command/response interpretation the setting of this bit effects the meaning of the ? c/r ? bit in the receive status byte ( rsta ). this status bit ? c/r ? should be interpreted after reception as follows: ? 0 ? (if ? cri ? = ? 1 ? ) ; ? 1 ? (if ? cri ? = ? 0 ? ) : command received ? 1 ? (if ? cri ? = ? 1 ? ) ; ? 0 ? (if ? cri ? = ? 0 ? ) : response received note: if 1-byte address field is selected in hdlc automode, rah1 must be set to 0x00 h . ral1 receive address 1 byte low the general function and its meaning depends on the selected hdlc operating mode: automode / address mode 2 (16-bit address) ral1 can be programmed with the value of the first individual low address byte. automode / address mode 2 (8-bit address) according to x.25 lap-b protocol, the address in ral1 is considered as the address of a ? command ? frame. rah2 receive address 2 byte high ral2 receive address 2 byte low value of the second individually programmable high/low address byte. if a 1-byte address field is selected, ral2 is considered as the address of a ? response ? frame according to x.25 lap-b protocol.
peb 20525 pef 20525 register description (amral1) data sheet 5-187 2000-09-14 register 66 amral1 mask receive address 1 low register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 44 h 94 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive mask address 1 (low) amral1 register 67 amrah1 mask receive address 1 high register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 45 h 95 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive mask address 1 (high) amrah1
peb 20525 pef 20525 register description (amral2) data sheet 5-188 2000-09-14 register 68 amral2 mask receive address 2 low register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 46 h 96 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive mask address 2 (low) amral2 register 69 amrah2 mask receive address 2 high register cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 47 h 97 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive mask address 2 (high) amrah2
peb 20525 pef 20525 register description (amrah2) data sheet 5-189 2000-09-14 amrah2 receive mask address 2 byte high amral2 receive mask address 2 byte low amrah1 receive mask address 1 byte high amral1 receive mask address 1 byte low setting a bit in this registers to ? 1 ? masks the corresponding bit in registers rah2 / ral2 / rah1 / ral1 . a masked bit position always matches when comparing the received frame address with registers rah2 / ral2 / rah1 / ral1 , allowing extended broadcast mechanism. bit = ? 0 ? the dedicated bit position is not masked. this bit position in the received address must match with the corresponding bit position in registers rah2 / ral2 / rah1 / ral1 to accept the frame. bit = ? 1 ? the dedicated bit position is masked. this bit position in the received address need not match with the corresponding bit position in registers rah2 / ral2 / rah1 / ral1 to accept the frame.
peb 20525 pef 20525 register description (rlcrl) data sheet 5-190 2000-09-14 register 70 rlcrl receive length check register (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 48 h 98 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive length limit rl(7:0) register 71 rlcrh receive length check register (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: 49 h 99 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 receive length check control receive length limit rce 0 0 0 0 rl(10:8)
peb 20525 pef 20525 register description (rlcrh) data sheet 5-191 2000-09-14 rce receive length check enable this bit is valid in hdlc mode only and enables/disables the receive length check function: rce = ? 0 ? no receive length check on received hdlc frames is performed. rce = ? 1 ? the receive length check is enabled. all bytes of a hdlc frame which are transferred to the receive fifo (depending on the selected protocol sub-mode and receive crc handling) are counted and checked against the maximum length check limit which is programmed in bit field ? rl ? . a frame exceeding the maximum length is treated as if it were aborted on the receive line ( ? rme ? interrupt and bit ? rab ? (receive abort) set in the rsta byte). in addition a ? flex ? interrupt is generated prior to ? rme ? , if enabled. note: the receive status byte ( rsta ) is part of the frame length checking. rl(10:0) receive length check limit this bit-field defines the receive length check limit (32..65536 bytes) if checking is enabled via bit ? rce ? : rl(10:0) the receive length limit is calculated by: limit rl 1 + 32 =
peb 20525 pef 20525 register description (isr0) data sheet 5-192 2000-09-14 register 72 isr0 interrupt status register 0 cpu accessibility: read only reset value: 00 h channel a channel b offset address: 50 h a0 h typical usage: updated by serocco-h read and evaluated by cpu bit76543210 isr0 rdo rfo pce rsc rpf rme rfs flex register 73 isr1 interrupt status register 1 cpu accessibility: read only reset value: 00 h channel a channel b offset address: 51 h a1 h typical usage: updated by serocco-h read and evaluated by cpu bit76543210 isr1 tin csc xmr xpr alls xdu suex 0
peb 20525 pef 20525 register description (isr2) data sheet 5-193 2000-09-14 register 74 isr2 interrupt status register 2 cpu accessibility: read only reset value: 00 h channel a channel b offset address: 52 h a2 h typical usage: updated by serocco-h read and evaluated by cpu bit76543210 isr2 000000pllacdsc
peb 20525 pef 20525 register description (isr2) data sheet 5-194 2000-09-14 rdo receive data overflow interrupt this bit is set to ? 1 ? , if receive data of the current frame got lost because of a scc receive fifo full condition. however the rest of the frame is received and discarded as long as the receive fifo remains full and is stored as soon as fifo space is available again. the receive status byte ( rsta ) of such a frame contains an ? rdo ? indication. in dma operation the ? rdo ? indication is also set in the receive byte count register rbch . rfo receive fifo overflow interrupt this bit is set to ? 1 ? , if the scc receive fifo is full and a complete frame must be discarded. this interrupt can be used for statistical purposes, indicating that the host was not able to service the scc receive fifo quickly enough, e.g. due to high bus latency. pce protocol error interrupt this bit is valid in hdlc automode only. it is set to ? 1 ? , if the receiver has detected a protocol error, i.e. one of the following events occured: an s- or i-frame was received with wrong n(r) counter value; an s-frame containing an information field was received. rsc receive status change interrupt this bit is valid in hdlc automode only. it is set to ? 1 ? , if a status change of the remote station receiver has been detected by receiving a s-frame with receiver ready (rr) or receiver not ready (rnr) indication. because only a status change is indicated via this interrupt, the current status can be evaluated by reading bit ? rrnr ? in status register starh . rpf receive pool full interrupt this bit is set to ? 1 ? if the rfifo threshold level, set with bit field ? rfth(1:0) ? in register ccr3h , is reached. default threshold level is 32 data bytes.
peb 20525 pef 20525 register description (isr2) data sheet 5-195 2000-09-14 rme receive message end interrupt this bit set to ? 1 ? indicates that the reception of one message is completed, i.e. either ? one message which fits into rfifo not exceeding the receive fifo threshold, or ? the last part of a message, all in all exceeding the receive fifo threshold is stored in the rfifo. the complete message length can be determined by reading the rbcl / rbch registers. the number of bytes stored in rfifo is given by the 5, 4, 2 or 1 least significant bits of register rbcl , depending on the selected rfifo threshold (bit field ? rfth(1:0) ? in register ccr3h ). additional frame status information is available in the rsta byte, stored in the rfifo as the last byte of each frame. note: after the rfifo contents have been read, an cmdrh :rmc command must be issued to free the rfifo for new receive data. rfs receive frame start interrupt this bit is set to ? 1 ? , if the beginning of a valid frame is detected by the receiver. a valid frame start is detected either if a valid address field is recognized (in all operating modes with address recognition) or if a start flag is recognized (in all operating modes with no address recognition). flex frame length exceeded interrupt this bit is set to ? 1 ? , if the frame length check feature is enabled and the current received frame is aborted because the programmed frame length limit was exceeded (refer to registers rlcrl / rlcrh for detailed description). tin timer interrupt this bit is set to ? 1 ? , if the internal timer was activated and has expired (refer also to description of timer registers timr0 .. timr3 ). csc cts status change this bit is set to ? 1 ? , if a transition occurs on signal cts . the current state of signal cts is monitored by status bit ? cts ? in status register starl . note: a transmit clock must be provided to detect a transition of cts .
peb 20525 pef 20525 register description (isr2) data sheet 5-196 2000-09-14 xmr transmit message repeat this bit is set to ? 1 ? , if transmission of the last frame has to be repeated (by software), because the scc has received a negative acknowledge to an i-frame (in hdlc automode operation); a collision occured after at least 14.5 bytes of data have been completely sent out, i.e. automatic re-transmission cannot be performed by the scc; cts signal was deasserted after at least 14.5bytes of data have been completely sent out. note: for easy recovery from a collision event (in bus configuration only), the scc transmit fifo should not contain more than one complete frame. this can be achieved by using the ? alls ? interrupt to control the corresponding transmit channel forwarding a new frame on all sent (alls) event only. xpr transmit pool ready interrupt this bit is set to ? 1 ? , if a transmitter reset command was executed successfully (command bit ? xres ? in register cmdrl ) and whenever the xfifo is able to accept new transmit data again. an ? xpr ? interrupt is not generated, if no sufficient transmit clock is available (depending on the selected clock mode). alls all sent interrupt this bit is set to ? 1 ? : if the last bit of the current hdlc frame is sent out via pin txd and no further frame is stored in the scc transmit fifo, i.e. the transmit fifo is empty (address mode 2/1/0); if an i-frame is sent out completely via pin txd and either a valid acknowledge s-frame has been received or a time-out condition occured because no valid acknowledge s-frame has been received in time (automode).
peb 20525 pef 20525 register description (isr2) data sheet 5-197 2000-09-14 xdu transmit data underrun interrupt this bit is set to ? 1 ? , if the current frame was terminated by the scc with an abort sequence, because neither a ? frame end ? indication was detected in the fifo (to complete the current frame) nor more data is available in the scc transmit fifo. note: the transmitter is stopped if this condition occurs. the xdu condition must be cleared by reading register isr1 , thus bit ? xdu ? should not be masked via register imr1 . suex signalling unit counter exceeded interrupt this bit is set to ? 1 ? , if 256 correct or incorrect su ? s have been received and the internal counter is reset to 0. plla dpll asynchronous interrupt this bit is only valid, if the receive clock is derived from the internal dpll and fm0, fm1 or manchester data encoding is selected (depending on the selected clock mode and data encoding mode). it is set to ? 1 ? if the dpll has lost synchronization. reception is disabled until synchronization has been regained again. if the transmitter is supplied with a clock derived from the dpll, transmission is also interrupted. cdsc carrier detect status change interrupt this bit is set to ? 1 ? , if a state transition has been detected at signal cd. because only a state transition is indicated via this interrupt, the current status can be evaluated by reading bit ? cd ? in status register starh . note: a receive clock must be provided to detect a transition of cd.
peb 20525 pef 20525 register description (imr0) data sheet 5-198 2000-09-14 register 75 imr0 interrupt mask register 0 cpu accessibility: read/write reset value: ff h channel a channel b offset address: 54 h a4 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 imr0 rdo rfo pce rsc rpf rme rfs flex register 76 imr1 interrupt mask register 1 cpu accessibility: read/write reset value: ff h channel a channel b offset address: 55 h a5 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 imr1 tin csc xmr xpr alls xdu suex 1
peb 20525 pef 20525 register description (imr2) data sheet 5-199 2000-09-14 register 77 imr2 interrupt mask register 2 cpu accessibility: read/write reset value: 03 h channel a channel b offset address: 56 h a6 h typical usage: written by cpu; read and evaluated by serocco-h bit76543210 imr2 000000pllacdsc
peb 20525 pef 20525 register description (imr2) data sheet 5-200 2000-09-14 (im) interrupt mask bits each scc interrupt event can generate an interrupt signal indication via pin int/int . each bit position of registers imr0 .. imr2 is a mask for the corresponding interrupt event in the interrupt status registers isr0 .. isr2 . masked interrupt events never generate an interrupt indication via pin int/int . bit = ? 0 ? the corresponding interrupt event is not masked and will generate an interrupt indication via pin int/int . bit = ? 1 ? the corresponding interrupt event is masked and will neither generate an interrupt vector nor an interrupt indication via pin int/int . moreover, masked interrupt events are: not displayed in the interrupt status registers isr0 .. isr2 if bit ? vis ? in register ccr0l is programmed to ? 0 ? . displayed in interrupt status registers isr0 .. isr2 if bit ? vis ? in register ccr0l is programmed to ? 1 ? . note: after reset, all interrupt events are masked. undefined bits must not be cleared to ? 0 ? . for detailed interrupt event description refer to the corresponding bit position in registers isr0 .. isr2 .
peb 20525 pef 20525 register description (rsta) data sheet 5-201 2000-09-14 the receive status byte ? rsta ? contains comprehensive status information about the last received frame (hdlc/ppp). the scc attaches this status byte to the receive data and thus it should be read from the rfifo. in hdlc/ppp modes the rsta value can optionally be read from this register address. in extended transparent mode this status field does not apply. register 78 rsta receive status byte cpu accessibility: read only reset value: 00 h channel a channel b offset address: 58 h a8 h typical usage: written by serocco-h to rfifo; read from rfifo and evaluated by cpu bit76543210 receive status byte vfr rdo crcok rab ha(1:0)/ su(1:0) c/r la
peb 20525 pef 20525 register description (rsta) data sheet 5-202 2000-09-14 vfr valid frame determines whether a valid frame has been received. vfr= ? 0 ? the received frame is invalid. an invalid frame is either a frame which is not an integer number of 8 bits (n * 8 bits) in length (e.g. 25 bits), or a frame which is too short, taking into account the operation mode selected via ccr2l (mds1, mds0, adm) and the selected crc algorithm ( ccr1l :c32) as follows: for ccr3h :drcrc = ? 0 ? (crc reception enabled): automode / address mode 2 (16-bit address) 4 bytes (crc-ccitt) or 6 (crc-32) automode / address mode 2 (8-bit address) 3 bytes (crc-ccitt) or 5 (crc-32) address mode 1: 3 bytes (crc-ccitt) or 5 (crc-32) address mode 0: 2 bytes (crc-ccitt) or 4 (crc-32) for ccr3h :drcrc = ? 1 ? (crc reception disabled): automode / address mode 2 (16-bit address): 2bytes automode / address mode 2 (8-bit address): 1byte address mode 1: 1byte address mode 0: 1byte note: shorter frames are not reported at all. vfr= ? 1 ? the received frame is valid. rdo receive data overflow rdo= ? 0 ? no receive data overflow has occurred. rdo= ? 1 ? a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr0 :rdo/ imr0 :rdo).
peb 20525 pef 20525 register description (rsta) data sheet 5-203 2000-09-14 crcok crc compare/check crcok= ? 0 ? crc check failed, received frame contains errors. crcok= ? 1 ? crc check ok; the received frame does not contain crc errors. rab receive message aborted rab= ? 0 ? no abort condition was detected during reception of the frame. rab= ? 1 ? the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. this bit is also set to ? 1 ? if the maximum receive byte count (set in registers rlcrl / rlcrh ) is reached. ha(1:0) high byte address compare significant only if an address mode with automatic address handling has been selected. in operating modes which provide high byte address recognition, serocco-h compares the high byte of a 2-byte address with the contents of two individually programmable addresses ( rah1 , rah2 ) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: ha(1:0)= ? 10 ? rah1 has been recognized. ha(1:0)= ? 00 ? rah2 has been recognized. ha(1:0)= ? 01 ? broadcast address has been recognized. if rah1 and rah2 contain identical values, a match is indicated by ha(1:0)= ? 10 ? . su(1:0) ss7 signaling unit type if signaling system #7 support is activated (see ccr3l register, bit ? ess7 ? ), the bit functions are defined as follows: su(1:0)= ? 00 ? not valid su(1:0)= ? 01 ? fill in signaling unit (fisu) detected su(1:0)= ? 10 ? link status signaling unit (lssu) detected su(1:0)= ? 11 ? message signaling unit (msu) detected
peb 20525 pef 20525 register description (rsta) data sheet 5-204 2000-09-14 c/r command/response significant only if 2-byte address mode has been selected. value of the c/r bit (bit 1 of high address byte) in the received frame. the interpretation depends on the setting of the ? cri ? bit in the rah1 register (see ? rah1 ? on page 184.). la low byte address compare significant in automode and address mode 2 only. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two addresses ( ral1 , ral2 ). la= ? 0 ? ral2 has been recognized. la= ? 1 ? ral1 has been recognized. according to the x.25 lapb protocol, ral1 is interpreted as the address of a command frame and ral2 is interpreted as the address of a response frame.
peb 20525 pef 20525 register description (rsta) data sheet 5-205 2000-09-14 5.2.3 channel specific dma registers each register description is organized in three parts: a head with general information about reset value, access type (read/write), channel specific offset address and usual handling; a table containing the bit information (name of bit positions); a section containing the detailed description of each bit.
peb 20525 pef 20525 register description (xbcl) data sheet 5-206 2000-09-14 register 79 xbcl transmit byte count (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: b8 h d2 h typical usage: written by cpu, evaluated by serocco-h bit76543210 xbc(7:0) register 80 xbch transmit byte count (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: b9 h d3 h typical usage: written by cpu, evaluated by serocco-h bit76543210 xme xf xif 0 xbc(11:8)
peb 20525 pef 20525 register description (xbch) data sheet 5-207 2000-09-14 xbc (11:0) transmit byte count this register is used in dma mode only, to program the length (1 ? 4096 bytes) of the next frame to be transmitted. the length of the block in number of bytes is: this allows the serocco-h to request the correct amount of dma cycles after an ? xf ? or ? xif ? command. xme transmit message end command only valid in external dma controller mode. this bit is identical to ? xme ? command bit (refer to register ? cmdrl ? on page 135 ). xf transmit frame command only valid in external dma controller mode. this bit is identical to ? xf ? command bit (refer to register ? cmdrl ? on page 135 ). xif transmit i-frame command only valid in external dma controller mode. this bit is identical to ? xif ? command bit (refer to register ? cmdrl ? on page 135 ). length xbc 1 + =
peb 20525 pef 20525 register description (rmbsl) data sheet 5-208 2000-09-14 register 81 rmbsl receive maximum buffer size (low byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: c4 h de h typical usage: written by cpu, evaluated by serocco-h bit76543210 receive maximum buffer size rmbs(7:0) register 82 rmbsh receive maximum buffer size (high byte) cpu accessibility: read/write reset value: 00 h channel a channel b offset address: c5 h df h typical usage: written by cpu, evaluated by serocco-h bit151413121110 9 8 receive maximum buffer size re drmbs 0 0 rmbs(11:8)
peb 20525 pef 20525 register description (rmbsh) data sheet 5-209 2000-09-14 re receive dma enable only valid if external dma controller support is enabled. self-clearing command bit: re= ? 0 ? the dma controller is not set up to forward receive data into a buffer in memory. re= ? 1 ? setting this bit to ? 1 ? enables the dma support logic to request the external dma controller to transfer receive data when available in rfifo. drmbs disable receive maximum buffer size (rmbs) check only valid if external dma controller support is enabled. drmbs= ? 0 ? evaluation of bit field rmbs(11:0) is enabled. drmbs= ? 1 ? evaluation of bit field rmbs(11:0) is disabled. rmbs(11:0) receive maximum buffer size only valid if external dma controller support is enabled. the size of the receive buffer in host memory can be set up in this bit field to ensure that request for dma transfers are inhibited when the maximum buffer size is reached. an rbf interrupt is generated (if unmasked) to inform the cpu. if the external dma controller supports this function, it can be disabled by setting bit ? drmbs ? to ? 1 ? .
peb 20525 pef 20525 register description (rbcl) data sheet 5-210 2000-09-14 register 83 rbcl receive byte count (low byte) cpu accessibility: read only reset value: 00 h channel a channel b offset address: c6 h e0 h typical usage: written by serocco-h, evaluated by cpu bit76543210 rbc(7:0) register 84 rbch receive byte count (high byte) cpu accessibility: read only reset value: 00 h channel a channel b offset address: c7 h e1 h typical usage: written by serocco-h, evaluated by cpu bit76543210 rbco 0 0 0 rbc(11:8)
peb 20525 pef 20525 register description (rbch) data sheet 5-211 2000-09-14 rbc(11:0) receive byte count this bit field determines the receive byte count (1..4095) of the currently received frame/block. rbco receive byte counter overflow only valid in dma controller mode. this bit indicates an overflow of the receive byte conter rbc(11:0), i.e. the receive frame length exceeded 4095 bytes.
peb 20525 pef 20525 register description (ver0) data sheet 5-212 2000-09-14 5.2.4 miscellaneous registers register 85 ver0 version register 0 cpu accessibility: read only reset value: 83 h offset address: ec h typical usage: evaluated by cpu bit76543210 manufacturer code fix ? 1 ? ver(7:0) register 86 ver1 version register 1 cpu accessibility: read only reset value: f0 h offset address: ed h typical usage: evaluated by cpu bit76543210 device code (bits 3 .. 0) manufacturer code ver(15:8)
peb 20525 pef 20525 register description (ver2) data sheet 5-213 2000-09-14 register 87 ver2 version register 2 cpu accessibility: read only reset value: 05 h offset address: ee h typical usage: evaluated by cpu bit76543210 device code (bits 11 .. 4) ver(23:16) register 88 ver3 version register 3 cpu accessibility: read only reset value: 20 h offset address: ef h typical usage: evaluated by cpu bit76543210 version number device code (bits 15 .. 12) ver(31:24)
peb 20525 pef 20525 register description data sheet 214 2000-09-14 ver(31:0) version register identical to 32 bit boundary scan id string. the 32 bit string consists of the bit fields: ver(31:28) 2 h version number ver(27:12) 005f h device code ver(11:0) 083 h manufacturer code (lsb fixed to ? 1 ? )
peb 20525 pef 20525 programming data sheet 215 2000-09-14 6programming 6.1 initialization after reset the cpu has to write a minimum set of registers and an optional set depending on the required features and operating modes. first, the following initialization steps must be taken: select serial protocol mode (refer to table 12 "protocol mode overview" on page 83 ), select encoding of the serial data (refer to chapter 3.2.13 ? data encoding ? on page 74 ), program the output characteristics of - pin txd (selected with bit ? ods ? in ? channel configuration register 1 (low byte) ? on page 143 ) and - interrupt pin int/int (selected with bit field ? ipc(1:0) ? in ? global mode register ? on page 112 ), choose a clock mode (refer to table 7 "overview of clock modes" on page 47 ). power-up the oscillator unit (with or without shaper) by re-setting bit gmode :oscpd to ? 0 ? , if appropriate ( gmode :dshp= ? 0 ? enables the shaper). the clock mode must be set before power-up ( ccr0h .pu). the cpu may switch the serocco-h between power-up and power-down mode. this has no influence upon the contents of the registers, i.e. the internal state remains stored. in power-down mode however, all internal clocks are disabled, no interrupts from the corresponding channel are forwarded to the cpu. this state can be used as a standby mode, when the channel is (temporarily) not used, thus substantially reducing power consumption. the serocco-h should usually be initialized in power-down mode. the need for programming further registers depends on the selected features (serial mode, clock mode specific features, operating mode, address mode, user demands). 6.2 interrupt mode 6.2.1 data transmission (interrupt driven) in transmit direction 2 32 byte fifo buffers (transmit pools) are provided for each channel. after checking the xfifo status by polling the transmit fifo write enable bit (bit ? xfw ? in starl register) or after a transmit pool ready ( ? xpr ? ) interrupt, up to 32 bytes may be entered by the cpu into the xfifo. the transmission of a packet can be started by issuing an ? xf ? or ? xif ? command via the cmdrl register. if enabled, a specified number of preambles (refer to registers ccr2h and preamb ) are sent out optionally before transmission of the current packet starts.
peb 20525 pef 20525 programming data sheet 216 2000-09-14 if the transmit command does not include an end of message indication ( cmdrl .xme), serocco-h will repeatedly request for the next data block by means of an ? xpr ? interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per ? xme ? command, after which packet transmission is finished correctly by appending the crc and closing flag sequence. consecutive packets may be transmitted as back-to-back packets and may even share a flag (enabled via ccr1l .sflg), if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of the end-of-message indiction ( ? xme ? ), the transmission of the packet is terminated with an abort sequence and the cpu is notified per interrupt ( isr1 .xdu, transmit data underrun). the packet may also be aborted per software at any time ( cmdrl .xres). the data transmission sequence, from the cpu ? s point of view, is outlined in figure 53 . figure 53 interrupt driven data transmission (flow diagram) start xfifo ready 'xpr' interrupt reset transmitter (cmdrl.xres) write data to xfifo (up to 32 bytes) end of message ? yes no issue command cmdrl.xf+.xme or cmdrl.xif+.xme issue command cmdrl.xf or cmdrl.xif action taken by cpu interrupt indication to cpu transmit serial data and append trailer transmit serial data action taken by the scc
peb 20525 pef 20525 programming data sheet 217 2000-09-14 6.2.2 data reception (interrupt driven) also 2 32 byte fifo buffers (receive pools) are provided for each channel in receive direction. there are different interrupt indications concerned with the reception of data: ? rpf ? (receive pool full) interrupt, indicating that a specified number of bytes (limited with the receive fifo threshold in register ccr3h , bit field ? rfth(1..0) ? ; default is 32 bytes) can be read from rfifo and the received message is not yet complete. ? rme ? (receive message end) interrupt, indicating that the reception of one message is completed, i.e. either - one message which fits into rfifo not exceeding the receive fifo threshold, or - the last part of a message, all in all exceeding the receive fifo threshold is stored in the rfifo. in addition to the message end ( ? rme ? ) interrupt the following information about the received packet is stored by serocco-h in special registers and/or rfifo: note: after the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing an ? rmc ? (receive message complete) command. the cpu has to handle the ? rpf ? interrupt before the complete 2 x 32- byte fifo is filled up with receive data which would cause a ? receive data overflow ? condition. the data reception sequence, from the cpu ? s point of view, is outlined in figure 54 . table 16 status information after rme interupt status information location length of received message registers rbch , rbcl crc result (good/bad) rsta register (or last byte of received data) valid frame (yes/no) rsta register (or last byte of received data) abort sequence recognized (yes/no) rsta register (or last byte of received data) data overflow (yes/no) rsta register (or last byte of received data) results from address comparison (with automatic address handling) rsta register (or last byte of received data) type of frame (command/response) (with automatic address handling) rsta register (or last byte of received data) type of signaling unit (in ss7 mode) rsta register (or last byte of received data)
peb 20525 pef 20525 programming data sheet 218 2000-09-14 1) a receive threshold of 32 bytes is the default for hdlc/ppp mode. it can be programmed with bit field rfth(1:0) in register . 2) the number of bytes stored in rfifo can be determined by evaluating the lower bits in register (depending on the selected receive threshold rfth(1:0)). figure 54 interrupt driven data reception (flow diagram) start wait for interrupt reset receiver (cmdrh.rres) activate receiver (ccr3l.rac) action taken by cpu interrupt indication to cpu 'rpf' interrupt read [32] 1) bytes from rfifo release rfifo (cmdrh.rmc) read registers rbcl, rbch (rc byte count) 'rme'/'tcd' interrupt read [rbcl % 32] 1), 2) bytes from rfifo
peb 20525 pef 20525 programming data sheet 219 2000-09-14 6.3 external dma supported mode the following table provides a definition of terms used in this chapter to describe the operation with external dma controller support. 6.3.1 data transmission (with external dma support) any packet transmission is prepared by initializing the external dma controller with the transmit buffer start address and writing the packet size in number of bytes to registers xbcl / xbch . now there are two possible scenarios: if the prepared transmit buffer in memory contains a complete packet, the start command for dma transmission is issued by setting bits ? xf ? and ? xme ? in register xbch to ? 1 ? . the dma support logic will request the external dma controller to transfer data into the xfifo . after the last byte has been transmitted, the protocol machine appends the trailer (e.g. crc and flag in hdlc), if applicable. the transmit dma transfer end (tdte) interrupt is generated (refer to figure 55 ). if a transmit packet is distributed over more than one transmit buffer in memory, the ? xf ? command (without setting the ? xme ? bit) forces serocco-h to request data transfers from the external dma controller from this buffer. a transmit dma transfer table 17 dma terminology packet a "packet" is a connected block of data bytes. if a receive status byte ( rsta ) is attached to data bytes, it is also considered as part of the packet. buffer a "buffer" is a limited space in memory that is reserved for dma reception/transmission. serocco-h can optionally keep track of predefined (receive) buffer limits and notify the cpu with an appropriate interrupt if this functionality is not provided by the external dma controller. a packet can go into one single buffer, or it can go fragmented into multiple buffers. block a "block" is the amount of data that is transfered from the memory to the xfifo (transmit dma transfer) or from the rfifo to the memory. the block size is 32 bytes by default. it can be lowered with the receive fifo threshold in register ccr3h , bit field ? rfth(1..0) ? . bus cycle a "bus cycle" corresponds to a single byte/word transfer. multiple bus cycles make up a block transfer. dma transfer a "dma transfer" is the movement of complete buffers and/or packets between the xfifo/rfifo and the memory by the external dma controller.
peb 20525 pef 20525 programming data sheet 220 2000-09-14 end (tdte) interrupt is generated whenever a block of bytes is completely transferred. for the last buffer, containing the end of the transmit packet, the ? xf ? command is issued together with bit ? xme ? set (refer to figure 56 ). after transmission is complete, the optional generation of the alls interrupt indicates that all transmit data has been sent on pin txd. note: in hdlc automode, the ? xf ? command may be replaced by the ? xif ? command in the same register, when transmission of an i-frame is desired. figure 55 dma transmit (single buffer per packet) xbc (prepare external dma controller with buffer base address) (write transmit byte count with command bit 'xf'+'xme') ... tfifo tfifo tfifo dma transfer of transmit data bytes tdte interrupt alls interrupt (optional) xbc (write transmit byte count with command bit 'xf'+'xme') ... packet n: packet (n+1): (prepare external dma controller with buffer base address) cpu / memory serocco-h
peb 20525 pef 20525 programming data sheet 221 2000-09-14 figure 56 fragmented dma transmission (multiple buffers per packet) xbc (write transmit byte count with command bit 'xf') ... tfifo tfifo tfifo dma transfer of transmit data bytes tdte interrupt alls interrupt (optional) xbc (write transmit byte count with command bit 'xf') ... tfifo tfifo tfifo dma transfer of transmit data bytes tdte interrupt xbc (write transmit byte count with command bit 'xf'+'xme') ... tfifo tfifo tfifo dma transfer of transmit data bytes tdte interrupt packet n, buffer 0: packet n, buffer 1: packet n, buffer m: (prepare external dma controller with buffer base address) (prepare external dma controller with buffer base address) (prepare external dma controller with buffer base address) cpu / memory serocco-h
peb 20525 pef 20525 programming data sheet 222 2000-09-14 6.3.2 data reception (with external dma support) the receive dma support logic is able to limit its requesting for data transfers to a byte count programmed in register rmbsl / rmbsh . if the external dma controller is capable of handling maximum receive buffer sizes itself, this feature can be disabled by setting bit rmbsh :drmbs to ? 1 ? . if a new packet is received by the scc, the dma support logic will request the external dma controller to move receive data out of the rfifo. now there are two possible scenarios: if the maximum buffer size programmed in register rmbsl / rmbsh has been transferred (only if rmbsh :drmbs = ? 0 ? ), serocco-h stops requesting for data transfers and a receive buffer full (rbf) interrupt is generated. the cpu now updates the receive buffer base address in the external dma controller and releases the receive dma control logic by setting the ? re ? bit in register rmbsh . optionally the maximum buffer size value can be updated with the same register write access. if the end of a received packet/block is part of the curent dma transfer, serocco-h generates a receive dma transfer end (rdte) interrupt and stops operation. the cpu now reads the received byte count from registers rbcl / rbch . the receive dma support logic will not continue requesting for data transfer until it is set up again with the ? re ? command in register rmbsh . if in packet oriented protocol modes (hdlc, ppp) the maximum receive buffer size rmbs is chosen to be larger than the expected receive packets, each buffer will contain the whole packet (see figure 57 ). in this case (or if rmbsh :drmbs = ? 1 ? ) a receive buffer full (rbf) interrupt will never occur, simplifying the software. to ensure that no packets exceeding the maximum buffer size are forwarded from the scc to the rfifo, the receive packet length should be limited with registers rlcrl / rlcrh .
peb 20525 pef 20525 programming data sheet 223 2000-09-14 figure 57 dma receive (single buffer per packet) figure 58 shows an example for fragmented reception of a packet larger than the prepared receive buffers in memory. in this case the length of the received packet is 199 bytes, each of the buffers in host memory is 128 bytes deep: rmbs (prepare external dma controller with receive buffer start address) ... rfifo rfifo rfifo dma transfer of all receive data bytes rdte interrupt ... packet 0: packet 1: rbc (issue 'r m c ' com m and) (set max. receive buffer size and issue 're' command) (prepare external dma controller with receive buffer start address) cmdr (read rbc register) cpu / memory serocco-h
peb 20525 pef 20525 programming data sheet 224 2000-09-14 figure 58 fragmented reception per dma (example) after the external dma controller is initialized with the base address of receive buffer #1 and the maximum buffer size rmbs is written to serocco-h, simultaneously activated with the ? re ? command, requesting of dma transfer from the rfifo to the receive buffer takes place in blocks of 32 bytes (unless changed with bit field ? rfth ? in register ccr3h ). after four 32-byte-blocks have been transferred, the first receive buffer is filled up completely with receive data. the serocco-h indicates this by generating the rbf interrupt. now the cpu has to provide the base address of the second receive buffer to the external dma controller and issue the ? re ? command to serocco-h again. this allows the external dma controller to continue data transfers into the second receive buffer. after another two 32-byte-blocks have been transferred, the dma request for the remaining 7 bytes (including the rsta byte) is generated to the external dma controller, follwed by the generation of the rdte interrupt. now the dma transfer is completed and software has to read the number of received bytes from the receive byte count registers rbcl / rbch . the following figure ( figure 59 ) gives the sequence of actions from both, the serocco-h and the cpu for this example (fragmented reception of 199 bytes into two receive buffers): 32 32 32 32 32 32 7 128 1 ... 199 bytes payload 128 1 1st packet fragment 2nd packet fragment ... receive buffers in memory packet
peb 20525 pef 20525 programming data sheet 225 2000-09-14 figure 59 fragmented reception sequence (example) rmbs (issue 're' command) rfifo rfifo rfifo dma transfer of 128 receive data bytes rbf interrupt ... packet 1, fragment 1: packet 2, fragment 1: rbc (read rbc register) rfifo rfifo rfifo dma transfer of 71 receive data bytes rdte interrupt packet 1, fragment 2: rfifo 32 32 32 32 32 32 7 rmbs (set m ax. receive buffer size to 128 bytes and issue 're' command) (prepare external dm a controller with receive buffer start address) (prepare external dm a controller with receive buffer start address) (prepare external dma controller with receive buffer start address) cmdr (issue 'r m c ' com m and) cpu / memory serocco-h
peb 20525 pef 20525 electrical characteristics data sheet 226 2000-09-14 7 electrical characteristics 7.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 operating range note: in the operating range, the functions given in the circuit description are fulfilled. parameter symbol limit values unit ambient temperature under bias peb pef t a t a 0 to 70 ? 40 to 85 c c storage temperature t stg ? 65 to 125 c ic supply voltage v dd3 ? 0.3 to 3.6 v voltage on any signal pin with respect to ground v s ? 0.4 to 5.5 v esd robustness 1) hbm: 1.5 k , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. v esd,hbm 2000 v parameter symbol limit values unit test condition min. max. ambient temperature peb pef t a t a 0 -40 70 85 c c junction temperature t j 0125 c supply voltage v dd3 3.0 3.6 v ground v ss 00v
peb 20525 pef 20525 electrical characteristics data sheet 227 2000-09-14 7.3 dc characteristics parameter symbol limit values unit notes min. max. input low voltage v il ? 0.4 0.8 v input high voltage v ih 2.0 2.1 5.5 5.5 v v v dd =3.3v v dd =3.6v output low voltage v ol 0.45 v i ol =7ma 1) i ol =2ma 2) 1) apply to the next pins: txda, txdb. 2) apply to all the i/o and o pins that do not appear in the list in note 1) , except xtal2. the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. output high voltage v oh 2.4 v i oh = ? 1.0 ma power supply current operational (average) i cc (av) 50 ma v dd =3.3v, t a =25 c, clk = 33 mhz, xtal = 20 mhz, inputs at v ss /v dd , no output loads power down (no clocks) i cc (pd) 0.01 ma v dd =3.3v, t a =25 c power dissipation p 150 mw v dd =3.3v, t a =25 c, clk = 33 mhz, xtal = 20 mhz, inputs at v ss /v dd , no output loads input leakage current i li 1
a v dd =3.3v, gnd = 0 v; inputs at v ss /v dd , no output loads output leakage current i lo 1
a v dd =3.3v, gnd = 0 v; v out =0v, v ddp +0.4
peb 20525 pef 20525 electrical characteristics data sheet 228 2000-09-14 7.4 ac characteristics interface pins t a = 0 to + 70 c; v dd3 = 3.3 v 0.3 v inputs are driven to 2.4 v for a logical ?1? and to 0.4 v for a logical ?0?. timing measurements are made at 2.0 v for a logical ?1? and at 0.8 v for a logical ?0?. the ac testing input/output waveforms are shown below. figure 60 input/output waveform for ac tests 7.5 capacitances interface pins table 18 capacitances t a = 25 c; v dd3 = 3.3 v 0.3 v, v ss = 0 v parameter symbol limit values unit test condition min. max. input capacitance c in 5 pf output capacitance c out 10 pf i/o-capacitance c io 15 pf its09800 = 50 pf load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points
peb 20525 pef 20525 electrical characteristics data sheet 229 2000-09-14 7.6 thermal package characteristics table 19 thermal package characteristics p-tqfp-100-3 parameter symbol value unit thermal package resistance junction to ambient airflow: ambient temperature: without airflow t a =-40 c ja(0,-40) 45.7 k/w without airflow t a =+25 c ja(0,25) 41.5 k/w airflow 1 m/s (~200 lfpm) t a =+25 c ja(1,25) 39.6 k/w airflow 2 m/s (~400 lfpm) t a =+25 c ja(2,25) 38.8 k/w airflow 3 m/s (~600 lfpm) t a =+25 c ja(3,25) 38.4 k/w table 20 thermal package characteristics p-lfbga-80-2 parameter symbol value unit thermal package resistance junction to ambient airflow: ambient temperature: without airflow t a =-40 c ja(0,-40) 56.1 k/w without airflow t a =+25 c ja(0,25) 50.6 k/w airflow 1 m/s (~200 lfpm) t a =+25 c ja(1,25) 48.2 k/w airflow 2 m/s (~400 lfpm) t a =+25 c ja(2,25) 47.2 k/w airflow 3 m/s (~600 lfpm) t a =+25 c ja(3,25) 46.6 k/w
peb 20525 pef 20525 electrical characteristics data sheet 230 2000-09-14 7.7 timing diagrams 7.7.1 microprocessor interface timing 7.7.1.1 microprocessor interface clock timing figure 61 microprocessor interface clock timing table 21 microprocessor interface clock timing no. parameter limit values unit min. max. 1 clk clock period 30 1) a clock supply is needed for read access to the on-chip interrupt status registers (isr, disr) and for general purpose port (gpp) operation. ns clk frequency 0 33 mhz 2 clk high time 11 ns 3 clk low time 11 ns clk 1 3 2
peb 20525 pef 20525 electrical characteristics data sheet 231 2000-09-14 7.7.1.2 infineon/intel bus interface timing figure 62 infineon/intel read cycle timing figure 63 infineon/intel write cycle timing a(7:0) bhe 1) cs d(7:0) d(15:8) 1) rd ready 4 6 5 7 8 14a 15a 17 11a 11 int 2) 16 10 14 15 (1) signals bhe and d(15:8) only available in 16-bit infineon/intel bus mode. (2) interrupt signal shown is push-pull, active high. same timings apply to push-pull, active low interrupt signal. in case of open-drain output the timing depends on external components. a(7:0) bhe 1) cs d(7:0) d(15:8) 1) wr ready 4 6 5 7 12 13 9 14a 15a 17 14 15 (1) signals bhe and d(15:8) only available in 16-bit infineon/intel bus mode.
peb 20525 pef 20525 electrical characteristics data sheet 232 2000-09-14 figure 64 infineon/intel dma read cycle timing figure 65 infineon/intel dma write cycle timing figure 66 infineon/intel multiplexed address timing cs 1) dack rd 18 drr last read access to rfifo (1) during dma cycles, fifo is selected with the corresponding fifo address plus cs asserted, or with dack asserted. (1) during dma cycles, fifo is selected with the corresponding fifo address plus cs asserted, or with dack asserted. cs 1) dack wr 19 drt last write access to xfifo a(7:0) bhe 1) ale wr rd 20 22 21 23 (1) signal bhe only available in 16-bit infineon/intel bus mode
peb 20525 pef 20525 electrical characteristics data sheet 233 2000-09-14 table 22 infineon/intel bus interface timing no. parameter limit values unit min. max. 4 active address to active rd /wr setup time 8 ns 5 inactive rd /wr to inactive address hold time 0 ns 6active cs to active rd /wr setup time 2 ns 7 inactive rd /wr to inactive cs hold time 0 ns 8rd active pulse width 30 1) 1) at least one rising clk edge must appear during read pulse active for interrupt status register (isr, disr) read. ns 9wr active pulse width 30 ns 10 active rd to valid data delay 20 ns 11 inactive rd to invalid data hold time 5 ns 11a inactive rd to data high impedance delay 25 ns 12 valid data to inactive wr setup time 6 ns 13 inactive wr to invalid data hold time 5 ns 14 active rd /wr to active ready delay 20 ns 14a active cs to driven ready delay 20 ns 15 inactive rd /wr to inactive ready delay 15 ns 15a inactive cs to ready high impedance delay 15 ns 16 inactive rd to inactive int/int delay 1 t clk 2) 2) t clk is the system clock (clk) period. 17 rd /wr inactive pulse width 30 ns 18 active rd to inactive drr delay 22 ns 19 active wr to inactive drt delay 22 ns 20 active address to inactive ale setup time 5 ns 21 inactive ale to inactive address hold time 5 ns 22 ale pulse width 30 ns 23 inactive ale to active rd /wr setup time 0 ns
peb 20525 pef 20525 electrical characteristics data sheet 234 2000-09-14 7.7.1.3 motorola bus interface timing figure 67 motorola read cycle timing figure 68 motorola write cycle timing a(7:0) a(7:1) 1) cs r/w d(7:0) d(15:8) 1) ds lds, uds 1) dtack 40 42 41 43 44 45 46 52a 53a 55 int 2) 49a 49 48 54 52 53 (1) signals lds , uds and d(15:8) only available in 16-bit motorola bus mode (2) interrupt signal shown is push-pull, active high. same timings apply to push-pull, active low interrupt signal. in case of open-drain output the timing depends on external components. a(7:0) a(7:1) 1) cs r/w d(7:0) d(15:8) 1) ds lds, uds 1) dtack 40 42 41 43 44 45 50 51 47 52a 53a 55 52 53 (1) signals lds , uds and d(15:8) only available in 16-bit motorola bus mode
peb 20525 pef 20525 electrical characteristics data sheet 235 2000-09-14 figure 69 motorola dma read cycle timing figure 70 motorola dma write cycle timing table 23 motorola bus interface timing no. parameter limit values unit min. max. 40 active address to active ds setup time 0 ns 41 inactive ds to inactive address hold time 0 ns 42 active cs to active ds setup time 0 ns 43 inactive ds to inactive cs hold time 0 ns 44 active r/w to active ds setup time 0 ns 45 inactive ds to inactive r/w hold time 0 ns 46 ds active pulse width (read access) 30 1) ns cs 1) dack ds 56 drr last read access to rfifo r/w (1) during dma cycles, fifo is selected with the corresponding fifo address plus cs asserted, or with dack asserted. cs 1) dack ds 57 drt last write access to xfifo r/w (1) during dma cycles, fifo is selected with the corresponding fifo address plus cs asserted, or with dack asserted.
peb 20525 pef 20525 electrical characteristics data sheet 236 2000-09-14 47 ds active pulse width (write access) 30 ns 48 active ds (read) to valid data delay 20 ns 49 inactive ds (read) to invalid data hold time 5 ns 49a inactive ds (read) to data high impedance delay 20 ns 50 valid data to inactive ds (write) setup time 10 ns 51 inactive ds (write) to invalid data hold time 10 ns 52 active ds to active dtack delay 20 ns 52a active cs to driving dtack delay 20 ns 53 inactive ds to inactive dtack delay 15 ns 53a inactive cs to dtack high impedance delay 15 ns 54 inactive ds (read) to inactive int/int delay 1 t clk 55 ds inactive pulse width 30 ns 56 active ds (read) to inactive drr delay 22 ns 57 active ds (write) to inactive drt delay 22 ns 1) at least one rising clk edge must appear during read data strobe active for interrupt status register (isr, disr) read. table 23 motorola bus interface timing (cont ? d) no. parameter limit values unit min. max.
peb 20525 pef 20525 electrical characteristics data sheet 237 2000-09-14 7.7.2 pcm serial interface timing 7.7.2.1 clock input timing figure 71 clock input timing table 24 clock input timing no. parameter limit values unit min. max. 81 rxclk clock period 80 ns 82 rxclk high time 32 ns 83 rxclk low time 32 ns 84 txclk clock period 80 ns 85 txclk high time 32 ns 86 txclk low time 32 ns 87 xtal1 clock period (internal oscillator used) 25 100 ns xtal1 clock period (ttl clock signal supplied) 25 ns 88 xtal1 high time (internal oscillator used) 12 46 ns xtal1 high time (ttl clock signal supplied) 12 ns 89 xtal1 low time (internal oscillator used) 12 46 ns xtal1 low time (ttl clock signal supplied) 12 ns rxclk txclk xtal1 81,84,87 82,85,88 83,86,89
peb 20525 pef 20525 electrical characteristics data sheet 238 2000-09-14 7.7.2.2 receive cycle timing figure 72 receive cycle timing table 25 receive cycle timing no. parameter limit values unit min. max. receive data rates externally clocked (hdlc) 0 12.5 mbit/s internally clocked (dpll modes) 0 2 mbit/s internally clocked (non dpll modes) 0 12.5 mbit/s 90 clock period externally clocked 80 ns internally clocked (dpll modes) 480 ns internally clocked (non dpll modes) 80 ns 91 rxd to rxclk setup time 5 ns 92 rxd to rxclk hold time 5 ns 90 91 92 91 92 93 94 receive clock (note 1) rxd (note 2) rxd (note 3) cd (note 4) 91 92 (1) whichever supplies the receive clock depending on the selected clock mode: externally clocked via rxclk or xtal1 or internally clocked via dpll or brg. (no edge relation can be measured if the internal receive clock is derived from the external clock source by division stages (brg) or dpll) (2) nrz, nrzi and manchester data encoding (3) fm0 and fm1 data encoding (4) if carrier detect auto start feature enabled (not for clock modes 1, 4 and 5)
peb 20525 pef 20525 electrical characteristics data sheet 239 2000-09-14 7.7.2.3 transmit cycle timing figure 73 transmit cycle timing 93 cd to rxclk rising edge setup time 5 ns 94 cd to rxclk falling edge hold time 5 ns table 25 receive cycle timing (cont ? d) no. parameter limit values unit min. max. 100 101 transmit clock (note1) txd (note2,5) txd (note3) txclk (note4) 106 102 103 104 105 106 102 103 cxd cts rts (note5) (1) whichever supplies the transmit clock depending on the selected clock mode: externally clocked via txclk, rxclk or xtal1 or internally clocked via dpll or brg. (no edge relation can be measured if the internal transmit clock is derived from the external clock source by division stages (brg) or dpll) (2) nrz, nrzi and manchester data encoding (3) fm0 and fm1 data encoding (4) if txclk output feature is enabled (only in some clock modes) (5) the timing is valid for non bus configuration modes and bus configuration mode 1. in bus configuration mode 2, txd and rts are right shifted for 0.5 txclk periods i.e. driven by the falling txclk edge.
peb 20525 pef 20525 electrical characteristics data sheet 240 2000-09-14 table 26 transmit cycle timing no. parameter limit values unit min. max. transmit data rates externally clocked 0 12.5 mbit/s internally clocked (dpll modes) 02mbit/s internally clocked (non dpll modes) 012.5mbit/s 100 clock period externally clocked 80 ns internally clocked (dpll modes) 480 ns internally clocked (non dpll modes) 80 ns 101 txd to txclk delay (nrz, nrzi encoding) 25 ns 102 txd to txclk delay (fm0, fm1, manchester encoding) 25 ns 103 txd to txclk(out) delay (output function enabled) 10 25 ns 104 cxd to txclk setup time 5 ns c ts to txclk setup time 5 ns 105 cxd to txclk hold time 5 ns c ts to txclk hold time 5 ns 106 rts to txclk delay (not bus configuration mode) 20 ns rts to txclk delay (bus configuration mode) 20 ns
peb 20525 pef 20525 electrical characteristics data sheet 241 2000-09-14 7.7.2.4 clock mode 1 strobe timing figure 74 clock mode 1 strobe timing table 27 clock mode 1 strobe timing no. parameter limit values unit min. max. 110 receive strobe to rxclk setup 5 ns 111 receive strobe to rxclk hold 5 ns 112 transmit strobe to rxclk setup 5 ns 113 transmit strobe to rxclk hold 5 ns 114 txd to rxclk delay 10 25 ns 115 txd to rxclk high impedance delay 10 25 ns 110 111 valid 112 113 114 114 115 115 rxclk cd (rxstrobe) rxd (note1) txclk (txstrobe) txd (note1,3) txd (note2,3) (1) no bus configuration mode and bus configuration mode 1 (2) bus configuration mode 2 (3) txd idle is either active high or high impedance if ? open drain ? output type is selected.
peb 20525 pef 20525 electrical characteristics data sheet 242 2000-09-14 7.7.2.5 clock mode 4 gating timing figure 75 clock mode 4 receive gating timing figure 76 clock mode 4 transmit gating timing table 28 clock mode 4 gating timing no. parameter limit values unit min. max. 140 rcg setup time 5 ns 141 rcg hold time 5 ns 142 rxd setup time 5 ns 143 rxd hold time 5 ns 145 tcg setup time 0 ns 146 tcg hold time 6 ns 147 txclk to txd delay 1) 1) note that the txd output is delayed for one additional clock with respect to the gating signal tcg ! 10 25 ns rxclk rcg rxd 140 141 142 143 txclk tcg txd 145 146 147
peb 20525 pef 20525 electrical characteristics data sheet 243 2000-09-14 7.7.2.6 clock mode 5 frame synchronisation timing figure 77 clock mode 5 frame synchronisation timing table 29 clock mode 5 frame synchronisation timing no. parameter limit values unit min. max. 130 sync pulse to rxclk setup time 10 ns 131 sync pulse to rxclk hold time 0 ns 132 txclkout to rxclk delay (time slot monitor) 10 27 ns 132 132 132 132 130 131 rxclk cd (fsc) txclk note1 txclk note2 (1) normal operation and bus configuration mode 1 (2) bus configuration mode 2
peb 20525 pef 20525 electrical characteristics data sheet 244 2000-09-14 7.7.3 reset timing figure 78 reset timing note: reset may be asserted and deasserted asynchronous to clk at any time. table 30 reset timing no. parameter limit values unit min. max. 150 reset pulse width 500 ns 151 number of clk cycles after r eset inactive 2 clk cycles power-on vdd3 clk reset 150 151
peb 20525 pef 20525 electrical characteristics data sheet 245 2000-09-14 7.7.4 jtag-boundary scan timing figure 79 jtag-boundary scan timing table 31 jtag-boundary scan timing no. parameter limit values unit min. max. 160 tck period 166 ns 161 tck high time 80 ns 162 tck low time 80 ns 163 tms setup time 30 ns 164 tms hold time 10 ns 165 tdi setup time 30 ns 166 tdi hold time 20 ns 167 tdo valid delay 60 ns 160 161 162 163 164 165 166 167 tck tms tdi trst tdo
peb 20525 pef 20525 test modes data sheet 246 2000-09-14 8 test modes 8.1 jtag boundary scan interface in the serocco-h a test access port (tap) controller is implemented. the essential part of the tap is a finite state machine (16 states) controlling the different operational modes of the boundary scan. both, tap controller and boundary scan, meet the requirements given by the jtag standard: ieee 1149.1. figure 80 gives an overview about the tap controller. figure 80 block diagram of test access port and boundary scan unit if no boundary scan operation is planned trst has to be connected with v ss . tms, tck and tdi do not need to be connected since pull-up transistors ensure high input levels in this case. nevertheless it would be a good practice to put these unused inputs to defined levels, using pull-up resistors. test handling (boundary scan operation) is performed via the pins tck (test clock), tms (test mode select), tdi (test data input) and tdo (test data output) when the tap controller is not in its reset state, i.e. trst is connected to v dd or it remains unconnected due to its internal pull-up. test data at tdi are loaded with a 4-mhz clock clock generation test access port (tap) tap controller - finite state machine - instruction register (3 bit) - test signal generator clock tck trst tms reset data in tdi test control tdo enable data out clock bs data in identification scan (32 bit) boundary scan (n bit) 6 control bus id data out ss data out n . . . . . . 1 2 pins
peb 20525 pef 20525 test modes data sheet 247 2000-09-14 signal connected to tck. ? 1 ? or ? 0 ? on tms causes a transition from one controller state to another; constant ? 1 ? on tms leads to normal operation of the chip. table 32 boundary scan sequence of serocco-h seq. no. pin i/o number of boundary scan cells constant value in, out, enable tdi 1ctsb i1 0 2ctsa i1 0 3cda i1 1 4rxda i1 0 5rxclka i1 0 6txda 2 00 7txclka 3 000 8rtsa o1 0 9 reset i1 0 10 int o2 01 11 gp10 i/o 3 011 12 gp9 i/o 3 111 13 gp8 i/o 3 000 14 internal i/o 3 010 15 gp6 i/o 3 000 16 internal i/o 3 001 17 internal i/o 3 1 00 18 internal i/o 3 000 19 a7 i/o 3 000 20 a6 i/o 3 000 21 a5 i/o 3 000 22 a4 i/o 3 000 23 a3 i/o 3 000 24 a2 i/o 3 000 25 a1 i/o 3 000 26 a0 i/o 3 000
peb 20525 pef 20525 test modes data sheet 248 2000-09-14 27 bm/ale i 1 0 28 cs i1 0 29 bhe i/o 3 000 30 w/r i/o 3 000 31 internal o 2 00 32 internal o 2 00 33 internal o 2 00 34 internal o 2 00 35 internal o 2 00 36 internal o 2 00 37 internal o 2 00 38 internal o 2 00 39 rd i/o 3 000 40 wr i/o 3 000 41 ready i/o 3 000 42 clk i 1 0 43 d0 i/o 2 00 44 d1 i/o 2 00 45 d2 i/o 2 00 46 d3 i/o 2 00 47 d4 i/o 2 00 48 d5 i/o 2 00 49 d6 i/o 2 00 50 d7 i/o 3 000 51 d8 i/o 2 00 52 d9 i/o 2 00 53 d10 i/o 2 00 54 d11 i/o 2 00 55 d12 i/o 2 00 56 d13 i/o 2 00 table 32 boundary scan sequence of serocco-h seq. no. pin i/o number of boundary scan cells constant value in, out, enable
peb 20525 pef 20525 test modes data sheet 249 2000-09-14 an input pin (i) uses one boundary scan cell (data in), an output pin (o) uses two cells (data out, enable) and an i/o-pin (i/o) uses three cells (data in, data out, enable). note that some functional output and input pins of serocco-h are tested as i/o pins in boundary scan, hence using three cells. the boundary scan unit of serocco-h contains a total of n = 158 scan cells. the right column of table 32 gives the initialization values of the cells. the desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via tdi (lsb first); see table 33 . 57 d14 i/o 2 00 58 d15 i/o 3 000 59 drta i/o 3 000 60 dacka i1 0 61 drra i/o 3 000 62 drrb i/o 3 000 63 drtb i/o 3 000 64 dackb i/o 3 000 65 rtsb o1 0 66 rxdb i 1 0 67 rxclkb i 1 0 68 txdb o 2 00 69 txclkb i/o 3 000 70 cdb i 1 0 71 ads o2 00 tdo table 32 boundary scan sequence of serocco-h seq. no. pin i/o number of boundary scan cells constant value in, out, enable
peb 20525 pef 20525 test modes data sheet 250 2000-09-14 extest is used to examine the interconnection of the devices on the board. in this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values ( ? 0 ? or ? 1 ? , according to table 32 ). then the contents of the boundary scan is shifted to tdo. at the same time the next scan vector is loaded from tdi. subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. intest supports internal testing of the chip, i.e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values ( ? 0 ? or ? 1 ? , according to table 32 ). the resulting boundary scan vector is shifted to tdo. the next test vector is serially loaded via tdi. then all input pins are updated for the following test cycle. note: in capture ir-state the code ? 001 ? is automatically loaded into the instruction register, i.e. if intest is wanted the shift ir-state does not need to be passed. sample/preload is a test mode which provides a snap-shot of pin levels during normal operation. idcode : a 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ? 1 ? . note: since in test logic reset state the code ? 011 ? is automatically loaded into the instruction register, the id code can easily be read out in shift dr state which is reached by tms = 0, 1, 0, 0. bypass : a bit entering tdi is shifted to tdo after one tck clock cycle. table 33 boundary scan test modes instruction (bit 2 ? 0) test mode 000 001 010 011 111 others extest (external testing) intest (internal testing) sample/preload (snap-shot testing) idcode (reading id code) bypass (bypass operation) handled like bypass tdi -> 0010 0000 0000 0101 1111 0000 1000 001 1 -> tdo
peb 20525 pef 20525 package outlines data sheet 251 2000-09-14 9 package outlines index marking 8 ? 0.5 0.1 8 0.3 min. 0.05 a1 a9 j1 8 x 0.8 = 6.4 0.8 c b a-b 0.13 80x ? 0.15 ? 0.08 c a 1.5 max. index marking 0.8 m + - 0.1 0.1 c 8 x 0.8 = 6.4 m p-lfbga-80-2 (low-profile fine-pitch ball grid gpa09236 sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm
peb 20525 pef 20525 package outlines data sheet 252 2000-09-14 p-tqfp-100-3 (plastic thin quad flat package) gpp09189 sorts of packing package outlines for tubes, trays etc. are contained in our data book ?package information?. dimensions in mm

▲Up To Search▲

Price & Availability of PEB20525F

	To Download PEB20525F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .